CY7C371I-110JC Cypress Semiconductor Corp, CY7C371I-110JC Datasheet - Page 2

• Manufacturer Part Number: CY7C371I-110JC
• Description: IC CPLD 32 MACROCELL 44-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultralogic™r

Specifications of CY7C371I-110JC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3.3V/5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1267

Pin Configurations
Functional Description
Finally, the CY7C371i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C371i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in a single pass
through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
handled by software and is invisible to the user.
Document #: 38-03032 Rev. **
LASH
LASH
370i family. The CY7C371i includes two logic blocks.
I/O
370i CPLDs. Note that product term allocation is
CLK
5
/SCLK
ISR
I/O
I/O
GND
I/O
I/O
I/O
I/O
0
/I
EN
10
11
I
6
1
8
7
0
9
7
8
9
10
11
12
13
14
15
16
17
18
6 5
19 20
4
21
3
Top View
22
(continued)
PLCC
2
LASH
23 24
1 44
25
370i logic block includes
43 42
26
27
41
28
40
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O
I/O
I/O
CLK
GND
I
I
I/O
I/O
I/O
3
2
7c371i–2
27
26
25
24
23
22
21
1
/SDI
/I
4
I/O Macrocell
Each of the macrocells on the CY7C371i has a separate as-
sociated I/O pin. The input to the macrocell is the sum of be-
tween 0 and 16 product terms from the product term allocator.
The macrocell includes a register that can be optionally by-
passed. It also has polarity control, and two global clocks to
trigger the register. The macrocell also features a separate
feedback path to the PIM so that the register can be buried if
the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
two logic blocks on the CY7C371i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with F
PCI Compliance
The F
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term dis-
tribution.
3.3V or 5.0V I/O operation
The F
and 5.0V systems. All devices have two sets of V
LASH
I/O
CLK
5
/SCLK
ISR
LASH
LASH
I/O
I/O
370i ensures compliance with the PCI AC specifications
GND
I/O
I/O
I/O
I/O
0
EN
/I
10
11
I
6
7
0
1
8
9
370i family can be configured to operate in both 3.3V
370i family of CMOS CPLDs are fully compliant with
1
2
3
4
5
6
7
8
9
10
11
44 43 42
12
13 14 15
41
Top View
16
40
TQFP
39 38 37
17
18 19 20
36
21
35
22
34
33
32
31
30
29
28
27
26
25
24
23
7c371i–3
I/O
I/O
I/O
I/O
CLK
GND
I
I
I/O
I/O
I/O
CY7C371i
3
2
LASH
27
26
25
24
23
22
21
1
/SDI
Page 2 of 12
/I
CC
4
370i.”
LASH
pins: one
370i