CY7C371I-110JC Cypress Semiconductor Corp, CY7C371I-110JC Datasheet - Page 4

• Manufacturer Part Number: CY7C371I-110JC
• Description: IC CPLD 32 MACROCELL 44-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultralogic™r

Specifications of CY7C371I-110JC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3.3V/5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1267

Electrical Characteristics
Capacitance
Inductance
Endurance Characteristics
Document #: 38-03032 Rev. **
Param.
V
V
V
V
V
I
I
I
I
I
I
I
I
C
C
L
N
Notes:
IX
OZ
OS
CC
BHL
BHH
BHLO
BHHO
2.
3.
4.
5.
6.
7.
8.
9.
OH
OHZ
OL
IH
IL
I/O
CLK
Parameter
Parameter
[10]
Parameter
See the last page of this specification for Group A subgroup testing information.
If V
I
When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered
significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold”
for additional information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect these parameters.
Measured with 16-bit counter programmed into each logic block.
OH
CCIO
= 2 mA, I
Output HIGH Voltage
with Output Enabled
Output HIGH Voltage
with Output Disabled
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short
Circuit Current
Power Supply Current
Input Bus Hold LOW
Sustaining Current
Input Bus Hold HIGH
Sustaining Current
Input Bus Hold LOW
Overdrive Current
Input Bus Hold HIGH
Overdrive Current
is not specified, the device can be operating in either 3.3V or 5V I/O mode; V
[8]
[8]
OL
Description
Maximum Reprogramming Cycles
= 2 mA for SDO.
Maximum Pin Inductance
Input Capacitance
Clock Signal Capacitance
[7,8]
Description
Description
Description
[8]
Over the Operating Range
[8]
V
V
V
Guaranteed Input Logical HIGH Voltage for all inputs
Guaranteed Input Logical LOW Voltage for all inputs
V
V
V
V
V
f = 1 MHz, V
V
V
V
V
CC
CC
CC
I
CC
CC
CC
CC
CC
CC
CC
CC
= Internal GND, V
= Min.
= Max.
= Min.
= Max., V
= Max., V
= Max., V
= Max., I
= Min., V
= Min., V
= Max.
= Max.
V
IN
OUT
IN
IL
IH
O
O
OUT
= GND, V
V
V
= 0.8V
= 5.0V at f= 1 MHz
= 2.0V
= GND or V
= 3.3V, Output Disabled
IN
IN
= 0 mA,
Test Conditions
= 0.5V
= 5.0V at f=1 MHz
= 5.0V at f = 1 MHz
I
Test Conditions
= V
Test Conditions
[2,3]
CC
CC
Normal Programming Conditions
[9]
O
I
I
I
I
=V
OH
OH
OH
OL
CC
Test Conditions
= 16 mA (Com’l/Ind)
= 3.2 mA (Com’l/Ind)
=
= 50 A (Com’l/Ind)
CC
, Output Disabled
=V
CCINT
A (Com’l/Ind)
[5]
Com’l/Ind.
Com’l “L” 66, 83
.
44-Lead TQFP
2
[4,5]
[6]
Min.
[6]
[4]
5
[4,5]
OUT
[4]
= 0.5V has been chosen to avoid test
Min.
+75
2.4
2.0
0.5
44-Lead PLCC
10
50
0
30
75
Max.
100
Max.
12
8
Typ.
–70
75
45
5
CY7C371i
Max.
–125
+500
Page 4 of 12
+10
+50
125
4.0
3.6
0.5
7.0
0.8
160
75
500
Cycles
Unit
Unit
pF
pF
Unit
nH
Unit
mA
mA
mA
V
V
V
V
V
V
A
A
A
A
A
A
A