DSP56303AG100 Freescale Semiconductor, DSP56303AG100 Datasheet - Page 11
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DSP56303AG100
Manufacturer Part Number
DSP56303AG100
Description
IC DSP 24BIT 100MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheet
1.DSP56303AG100.pdf
(108 pages)
Specifications of DSP56303AG100
Interface
Host Interface, SSI, SCI
Clock Rate
100MHz
Non-volatile Memory
ROM (576 B)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Package
144LQFP
Maximum Speed
100 MHz
Ram Size
24 KB
Device Million Instructions Per Second
100 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSP56303AG100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
DSP56303AG100B1
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
DSP56303AG100R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After
RESET is deasserted, these inputs are hardware interrupt request lines.
Freescale Semiconductor
RESET
MODA
IRQA
MODB
IRQB
MODC
IRQC
MODD
IRQD
Note: These signals are all 5 V tolerant.
Signal Name
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
State During
Reset
Table 1-9.
DSP56303 Technical Data, Rev. 11
Reset—Places the chip in the Reset state and resets the internal phase
generator. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET signal is
deasserted, the initial chip operating mode is latched from the MODA, MODB,
MODC, and MODD inputs. The RESET signal must be asserted after powerup.
Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request A—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the STOP or WAIT standby
state and IRQA is asserted, the processor exits the STOP or WAIT state.
Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state and
IRQB is asserted, the processor exits the WAIT state.
Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request C—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state and
IRQC is asserted, the processor exits the WAIT state.
Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request D—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state and
IRQD is asserted, the processor exits the WAIT state.
Interrupt and Mode Control
Signal Description
Interrupt and Mode Control
1-7