MSC8126TVT6400 Freescale Semiconductor, MSC8126TVT6400 Datasheet - Page 23

• Manufacturer Part Number: MSC8126TVT6400
• Description: IC DSP QUAD 16B 400MHZ 431FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8126TVT6400

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Device Core Size: 16b
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.1/1.1/1.2/1.2/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 431
• Package Type: FCBGA
• For Use With: MSC8126ADSE - KIT ADVANCED DEV SYSTEM 8126
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the
Freescale Semiconductor
Notes:
No.
No.
11a
11b
11d
15a
15b
11c
13
14
30
10
12
16
17
18
1
1
2
Hold time for all signals after the 50% level of the REFCLK rising edge
ARTRY/ABB set-up time before the 50% level of the REFCLK rising
edge
DBG/DBB/BG/BR/TC set-up time before the 50% level of the
REFCLK rising edge
AACK set-up time before the 50% level of the REFCLK rising edge
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
•
•
Data bus set-up time before REFCLK rising edge in Normal mode
•
•
Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
•
•
DP set-up time before the 50% level of the REFCLK rising edge
•
•
TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
•
•
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
•
•
PUPMWAIT signal set-up time before the 50% level of the REFCLK
rising edge
IRQx setup time before the 50% level; of the REFCLK rising edge
IRQx minimum pulse width
1.
2.
3.
Minimum delay from the 50% level of the REFCLK for all signals
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
Guaranteed by design
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Characteristic
Characteristic
3
Table 15. AC Timing for SIU Outputs
Table 14. AC Timing for SIU Inputs
3
6.0 + T
133
0.5
3.0
3.3
2.9
3.4
4.0
1.8
4.0
2.0
7.3
2.0
6.1
3.6
5.0
3.5
4.4
3.7
4.0
Ref = CLKIN
133
REFCLK
Value for Bus Speed in MHz
Value for Bus Speed in MHz
0.8
Ref = CLKIN
6.0 + T
166
166
0.5
3.0
3.3
2.9
3.4
4.0
1.7
4.0
2.0
7.3
2.0
6.1
3.6
5.0
3.5
4.4
3.7
4.0
0.8
REFCLK
Electrical Characteristics
Ref = CLKOUT
6.0 + T
CLKOUT
REFCLK
133
Ref =
1.0
133
0.5
3.0
3.3
2.9
3.4
4.0
1.8
4.0
2.0
7.3
2.0
6.1
3.8
5.0
3.5
4.4
3.7
4.0
REFCLK
rising edge.
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23