MSC8126TVT6400 Freescale Semiconductor, MSC8126TVT6400 Datasheet - Page 28

IC DSP QUAD 16B 400MHZ 431FCPBGA

MSC8126TVT6400

Manufacturer Part Number
MSC8126TVT6400
Description
IC DSP QUAD 16B 400MHZ 431FCPBGA
Manufacturer
Freescale Semiconductor
Series
MSC81xx StarCorer
Type
SC140 Corer
Datasheet

Specifications of MSC8126TVT6400

Interface
DSI, Ethernet, RS-232
Clock Rate
400MHz
Non-volatile Memory
External
On-chip Ram
1.436MB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
431-FCPBGA
Device Core Size
16b
Clock Freq (max)
400MHz
Mips
400
Device Input Clock Speed
400MHz
Operating Supply Voltage (typ)
1.1/1.1/1.2/1.2/3.3V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
431
Package Type
FCBGA
For Use With
MSC8126ADSE - KIT ADVANCED DEV SYSTEM 8126
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MSC8126TVT6400
Manufacturer:
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Part Number:
MSC8126TVT6400
Manufacturer:
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Quantity:
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Electrical Characteristics
2.5.6
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
28
Notes:
No.
100
101
102
103
104
105
106
107
108
109
110
111
112
201
202
Attributes
Attributes
Read/Write data strobe deassertion width:
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedance
Output data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedance
Output data valid to HTA assertion
Read/Write data strobe assertion to HTA valid
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
Read/Write data strobe assertion width
Host data input set-up time before write data strobe deassertion
Host data input hold time after write data strobe deassertion
1.
2.
3.
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
1.1 V core
1.2 V core
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
1.1 V core
1.2 V core
DSI Timing
Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
All values listed in this table are tested or guaranteed by design.
1
1
set-up time before strobe (HWBS[n]) assertion
hold time after data strobe deassertion
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Characteristics
Table 18. DSI Asynchronous Mode Timing
2
5 + (1.5 × T
5 + (2.5 × T
1.8 + T
1.8 + T
1.8 + T
5 + T
Min
1.5
1.3
2.0
2.2
2.2
3.2
1.0
1.7
1.5
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
)
)
5 + (1.5 × T
5 + (2.5 × T
Freescale Semiconductor
5 + T
Max
8.5
7.4
6.7
6.5
6.5
REFCLK
REFCLK
REFCLK
)
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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