ADSP-BF535PKB-350 Analog Devices Inc, ADSP-BF535PKB-350 Datasheet - Page 5

• Manufacturer Part Number: ADSP-BF535PKB-350
• Description: IC DSP CONTROLLER 16BIT 260 BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF535PKB-350

• Rohs Status: RoHS non-compliant
• Interface: PCI, SPI, SSP, UART, USB
• Clock Rate: 350MHz
• Non-volatile Memory: External
• On-chip Ram: 308kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.60V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 260-BGA
• Device Core Size: 32b
• Architecture: Modified Harvard
• Format: Floating Point
• Clock Freq (max): 350MHz
• Device Input Clock Speed: 350MHz
• Program Memory Size: Not RequiredKB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

The L1 memory system is the primary highest performance
memory available to the Blackfin processor core. The L2 memory
provides additional capacity with slightly lower performance.
Lastly, the off-chip memory system, accessed through the
External Bus Interface Unit (EBIU), provides expansion with
SDRAM, flash memory, and SRAM, optionally accessing more
than 768M bytes of external physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal L1/L2 memories and the external
memory spaces (including PCI memory space).
Internal (On-Chip) Memory
The ADSP-BF535 Blackfin processor has four blocks of on-chip
memory providing high bandwidth access to the core.
The first is the L1 instruction memory consisting of 16K bytes
of 4-Way set-associative cache memory. In addition, the memory
may be configured as an SRAM. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of 16K bytes each. Each L1 data memory
bank can be configured as one Way of a 2-Way set-associative
cache or as an SRAM, and is accessed at full speed by the core.
The third memory block is a 4K byte scratch pad RAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM (it cannot be configured as cache memory and is
not accessible via DMA).
The fourth on-chip memory system is the L2 SRAM memory
array which provides 256K bytes of high speed SRAM at the full
bandwidth of the core, and slightly longer latency than the L1
memory banks. The L2 memory is a unified instruction and data
memory and can hold any mixture of code and data required by
the system design.
The Blackfin processor core has a dedicated low latency 64-bit
wide datapath port into the L2 SRAM memory.
External (Off-Chip) Memory
External memory is accessed via the External Bus Interface Unit
(EBIU). This interface provides a glueless connection to up to
four banks of synchronous DRAM (SDRAM) as well as up to
four banks of asynchronous memory devices including flash,
EPROM, ROM, SRAM, and memory-mapped I/O devices.
The PC133 compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank
containing between 16M bytes and 128M bytes providing access
to up to 512M bytes of SDRAM. Each bank is independently
programmable and is contiguous with adjacent banks regardless
of the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory while
allowing the core to view all SDRAM as a single, contiguous,
physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
REV. A
–5–
64 Mbyte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with
64M bytes of memory.
PCI
The PCI bus defines three separate address spaces, which are
accessed through windows in the ADSP-BF535 Blackfin
processor memory space. These spaces are PCI memory, PCI
I/O, and PCI configuration.
In addition, the PCI interface can either be used as a bridge from
the processor core as the controlling CPU in the system, or as a
host port where another CPU in the system is the host and the
ADSP-BF535 is functioning as an intelligent I/O device on the
PCI bus.
When the ADSP-BF535 Blackfin processor acts as the system
controller, it views the PCI address spaces through its mapped
windows and can initialize all devices in the system and maintain
a map of the topology of the environment.
The PCI memory region is a 4 Gbyte space that appears on the
PCI bus and can be used to map memory I/O devices on the bus.
The ADSP-BF535 Blackfin processor uses a 128 Mbyte window
in memory space to see a portion of the PCI memory space. A
base address register is provided to position this window
anywhere in the 4 Gbyte PCI memory space while its position
with respect to the processor addresses remains fixed.
The PCI I/O region is also a 4 Gbyte space. However, most
systems and I/O devices only use a 64 Kbyte subset of this space
for I/O mapped addresses. The ADSP-BF535 Blackfin processor
implements a 64K byte window into this space along with a base
address register which can be used to position it anywhere in the
PCI I/O address space, while the window remains at the same
address in the processor's address space.
PCI configuration space is a limited address space, which is used
for system enumeration and initialization. This address space is
a very low performance communication mode between the
processor and PCI devices. The ADSP-BF535 Blackfin
processor provides a one-value window to access a single data
value at any address in PCI configuration space. This window is
fixed and receives the address of the value, and the value if the
operation is a write. Otherwise, the device returns the value into
the same address on a read operation.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4 Gbyte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for setup
and control of the on-chip peripherals outside of the core. The
core MMRs are accessible only by the core and only in supervisor
mode and appear as reserved space by on-chip peripherals, as
well as external devices accessing resources through the PCI bus.
The system MMRs are accessible by the core in supervisor mode
and can be mapped as either visible or reserved to other devices,
depending on the system protection model desired.
ADSP-BF535