ADSP-BF535PKB-350 Analog Devices Inc, ADSP-BF535PKB-350 Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF535PKB-350
• Description: IC DSP CONTROLLER 16BIT 260 BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF535PKB-350

• Rohs Status: RoHS non-compliant
• Interface: PCI, SPI, SSP, UART, USB
• Clock Rate: 350MHz
• Non-volatile Memory: External
• On-chip Ram: 308kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.60V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 260-BGA
• Device Core Size: 32b
• Architecture: Modified Harvard
• Format: Floating Point
• Clock Freq (max): 350MHz
• Device Input Clock Speed: 350MHz
• Program Memory Size: Not RequiredKB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF535
Booting
The ADSP-BF535 Blackfin processor contains a small boot
kernel, which configures the appropriate peripheral for booting.
If the ADSP-BF535 Blackfin processor is configured to boot from
boot ROM memory space, the processor starts executing from
the on-chip boot ROM. For more information, see
Modes on Page
Event Handling
The event controller on the ADSP-BF535 Blackfin processor
handles all asynchronous and synchronous events to the proces-
sor. The ADSP-BF535 Blackfin processor provides event
handling that supports both nesting and prioritization. Nesting
allows multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher-priority event
takes precedence over servicing of a lower priority event. The
controller provides support for five different types of events:
Each event has an associated register to hold the return address
and an associated return-from-event instruction. The state of the
processor is saved on the supervisor stack, when an event is
triggered.
The ADSP-BF535 Blackfin processor event controller consists
of two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
Reset—This event resets the processor.
Non-Maskable Interrupt (NMI)—The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly
shutdown of the system.
Exceptions—Events that occur synchronously to program
flow, for example, the exception will be taken before the
instruction is allowed to complete. Conditions such as
data alignment violations, undefined instructions, and so
on, cause exceptions.
Interrupts—Events that occur asynchronously to
program flow. They are caused by timers, peripherals,
input pins, explicit software instructions, and so on.
14.
Booting
–6–
support the peripherals of the ADSP-BF535 Blackfin processor.
Table 1
in the Event Vector Table (EVT), and lists their priorities.
Table 1. Core Event Controller (CEC)
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF535 Blackfin processor provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the
Interrupt Assignment Registers (IAR).
inputs into the SIC and the default mappings into the CEC.
Table 2. System Interrupt Controller (SIC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Peripheral Interrupt
Event
Real-Time Clock
Reserved
USB
PCI Interrupt
SPORT 0 Rx DMA
SPORT 0 Tx DMA
SPORT 1 Rx DMA
SPORT 1 Tx DMA
SPI 0 DMA
SPI 1 DMA
UART 0 Rx
UART 0 Tx
UART 1 Rx
UART 1 Tx
Timer 0
Timer 1
Timer 2
GPIO Interrupt A
GPIO Interrupt B
describes the inputs to the CEC, identifies their names
Event Class
Emulation/Test
Reset
Non-Maskable
Exceptions
Global Enable
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
Peripheral
Interrupt ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Table 2
describes the
EVT Entry
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Default
Mapping
IVG7
IVG7
IVG7
IVG8
IVG8
IVG8
IVG8
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
REV. A