EPF6016TC144-3N Altera, EPF6016TC144-3N Datasheet - Page 18
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EPF6016TC144-3N
Manufacturer Part Number
EPF6016TC144-3N
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6016TC144-3N
Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Family Name
FLEX 6000
Number Of Usable Gates
16000
Number Of Logic Blocks/elements
1320
# I/os (max)
117
Frequency (max)
125MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
5V
Logic Cells
1320
Device System Gates
16000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Total Ram Bits
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1956
EPF6016TC144-3N
EPF6016TC144-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6016TC144-3N
Manufacturer:
ALTERA42
Quantity:
1 341
Part Number:
EPF6016TC144-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 9. FastTrack Interconnect Architecture
Note:
(1)
18
Adjacent
To/From
LAB
For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices,
n = 186 channels and m = 30 channels.
10
10
5
Row Interconnect (n Channels) (1)
5
5
2
Local Interconnect (32 Channels)
10
10
10
5
The FastTrack Interconnect consists of column and row interconnect
channels that span the entire device. Each row of LABs is served by a
dedicated row interconnect, which routes signals between LABs in the
same row, and also routes signals from I/O pins to LABs. Additionally,
the local interconnect routes signals between LEs in the same LAB and in
adjacent LABs. The column interconnect routes signals between rows and
routes signals from I/O pins to rows.
LEs 1 through 5 of an LAB drive the local interconnect to the right, while
LEs 6 through 10 drive the local interconnect to the left. The DATA1 and
DATA3 inputs of each LE are driven by the local interconnect to the left;
DATA2 and DATA4 are driven by the local interconnect to the right. The
local interconnect also routes signals from LEs to I/O pins.
an overview of the FLEX 6000 interconnect architecture. LEs in the first
and last columns have drivers on both sides so that all LEs in the LAB can
drive I/O pins via the local interconnect.
5
22
2
5
through
through
LE 10
LE 1
LE 6
LE 5
5
5
10
10
10
10
5
20
5
5
Column Interconnect (m Channels) (1)
2
22
5
10
10
10
5
2
5
through
through
LE 10
LE 1
LE 6
LE 5
5
5
10
10
10
10
5
20
Altera Corporation
Figure 9
10
10
5
shows
To/From
Adjacent
LAB