EPF6016TC144-3N Altera, EPF6016TC144-3N Datasheet - Page 36

• Manufacturer Part Number: EPF6016TC144-3N
• Description: IC FLEX 6000 FPGA 16K 144-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6016TC144-3N

• Number Of Logic Elements/cells: 1320
• Number Of Labs/clbs: 132
• Number Of I /o: 117
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # I/os (max): 117
• Frequency (max): 125MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1956; EPF6016TC144-3N

FLEX 6000 Programmable Logic Device Family Data Sheet
Timing Model
36
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■
■
■
■
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the Simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
Figure 19
routing paths to and from the various elements of the FLEX 6000 device.
LE register clock-to-output delay (t
Routing delay (t
LE LUT delay (t
LE register setup time (t
shows the overall timing model, which maps the possible
DATA_TO_REG
ROW +
t
LOCAL
SU
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)
CO +
t
REG_TO_OUT
Altera Corporation
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