EPF6016TC144-3N Altera, EPF6016TC144-3N Datasheet - Page 38

• Manufacturer Part Number: EPF6016TC144-3N
• Description: IC FLEX 6000 FPGA 16K 144-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6016TC144-3N

• Number Of Logic Elements/cells: 1320
• Number Of Labs/clbs: 132
• Number Of I /o: 117
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # I/os (max): 117
• Frequency (max): 125MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1956; EPF6016TC144-3N

FLEX 6000 Programmable Logic Device Family Data Sheet
38
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t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
REG_TO_REG
CASC_TO_REG
CARRY_TO_REG
DATA_TO_REG
CASC_TO_OUT
CARRY_TO_OUT
DATA_TO_OUT
REG_TO_OUT
SU
H
CO
CLR
C
LD_CLR
CARRY_TO_CARRY
REG_TO_CARRY
DATA_TO_CARRY
CARRY_TO_CASC
CASC_TO_CASC
REG_TO_CASC
DATA_TO_CASC
CH
CL
Table 19. LE Timing Microparameters
Symbol
LUT delay for LE register feedback in carry chain
Cascade-in to register delay
Carry-in to register delay
LE input to register delay
Cascade-in to LE output delay
Carry-in to LE output delay
LE input to LE output delay
Register output to LE output delay
LE register setup time before clock; LE register recovery time after
asynchronous clear
LE register hold time after clock
LE register clock-to-output delay
LE register clear delay
LE register control signal delay
Synchronous load or clear delay in counter mode
Carry-in to carry-out delay
Register output to carry-out delay
LE input to carry-out delay
Carry-in to cascade-out delay
Cascade-in to cascade-out delay
Register-out to cascade-out delay
LE input to cascade-out delay
LE register clock high time
LE register clock low time
Tables 19
microparameters, which are expressed as worst-case values. Using hand
calculations, these parameters can be used to estimate design
performance. However, before committing designs to silicon, actual
worst-case performance should be modeled using timing simulation and
timing analysis.
parameters.
through
Note (1)
Tables 22
21
Parameter
describe the FLEX 6000 internal timing
and
23
describe FLEX 6000 external timing
Altera Corporation
Conditions