EPF6024AQC208-3N Altera, EPF6024AQC208-3N Datasheet - Page 18

• Manufacturer Part Number: EPF6024AQC208-3N
• Description: IC FLEX 6000 FPGA 24K 208-PQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024AQC208-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 171
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 171
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1957; EPF6024AQC208-3N

FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 9. FastTrack Interconnect Architecture
Note:
(1)
18
Adjacent
To/From
LAB
For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices,
n = 186 channels and m = 30 channels.
10
10
5
Row Interconnect (n Channels) (1)
5
5
2
Local Interconnect (32 Channels)
10
10
10
5
The FastTrack Interconnect consists of column and row interconnect
channels that span the entire device. Each row of LABs is served by a
dedicated row interconnect, which routes signals between LABs in the
same row, and also routes signals from I/O pins to LABs. Additionally,
the local interconnect routes signals between LEs in the same LAB and in
adjacent LABs. The column interconnect routes signals between rows and
routes signals from I/O pins to rows.
LEs 1 through 5 of an LAB drive the local interconnect to the right, while
LEs 6 through 10 drive the local interconnect to the left. The DATA1 and
DATA3 inputs of each LE are driven by the local interconnect to the left;
DATA2 and DATA4 are driven by the local interconnect to the right. The
local interconnect also routes signals from LEs to I/O pins.
an overview of the FLEX 6000 interconnect architecture. LEs in the first
and last columns have drivers on both sides so that all LEs in the LAB can
drive I/O pins via the local interconnect.
5
22
2
5
through
through
LE 10
LE 1
LE 6
LE 5
5
5
10
10
10
10
5
20
5
5
Column Interconnect (m Channels) (1)
2
22
5
10
10
10
5
2
5
through
through
LE 10
LE 1
LE 6
LE 5
5
5
10
10
10
10
5
20
Altera Corporation
Figure 9
10
10
5
shows
To/From
Adjacent
LAB