EPF6024AQC208-3N Altera, EPF6024AQC208-3N Datasheet - Page 29

• Manufacturer Part Number: EPF6024AQC208-3N
• Description: IC FLEX 6000 FPGA 24K 208-PQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024AQC208-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 171
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 171
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1957; EPF6024AQC208-3N

Altera Corporation
f
The instruction register length for FLEX 6000 devices is three bits.
shows the boundary-scan register length for FLEX 6000 devices.
FLEX 6000 devices include a weak pull-up on JTAG pins.
See
Devices)
Figure 16
Figure 16. JTAG Waveforms
Table 10
devices.
Captured
Table 9. FLEX 6000 Device Boundary-Scan Register Length
Driven
Signal
Signal
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
to Be
to Be
TMS
TDO
TCK
TDI
for more information.
shows the JTAG timing parameters and values for FLEX 6000
shows the timing requirements for the JTAG signals.
t
EPF6010A
EPF6016
EPF6016A
EPF6024A
JCH
Device
t
t
FLEX 6000 Programmable Logic Device Family Data Sheet
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
JPCO
JSCO
t
JPSU
Boundary-Scan Register Length
t
t
JSXZ
JPH
522
621
522
666
t
JPXZ
Table 9
29