EPF6024AQC208-3N Altera, EPF6024AQC208-3N Datasheet - Page 2

• Manufacturer Part Number: EPF6024AQC208-3N
• Description: IC FLEX 6000 FPGA 24K 208-PQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024AQC208-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 171
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 171
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1957; EPF6024AQC208-3N

FLEX 6000 Programmable Logic Device Family Data Sheet
...and More
Features
2
EPF6010A
EPF6016
EPF6016A
EPF6024A
Table 2. FLEX 6000 Package Options & I/O Pin Count
Device
100-Pin
TQFP
71
81
FineLine BGA
100-Pin
■
■
■
■
■
81
Powerful I/O pins
–
–
–
Flexible interconnect
–
–
–
–
–
Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800
Flexible package options
–
–
–
–
Additional design entry and simulation support provided by
EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules
(LPM), Verilog HDL, VHDL, DesignWare components, and other
interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, VeriBest, and Viewlogic
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
Fast path from register to I/O pin for fast clock-to-output time
FastTrack
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed, high-fan-
in logic functions (automatically used by software tools and
megafunctions)
Tri-state emulation that implements internal tri-state networks
Four low-skew global paths for clock, clear, preset, or logic
signals
Available in a variety of packages with 100 to 256 pins, including
the innovative FineLine BGA
SameFrame
across device densities and pin counts
Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and
ball-grid array (BGA) packages (see
Footprint- and pin-compatibility with other FLEX 6000 devices
in the same package
144-Pin
TQFP
102
117
117
117
®
Interconnect continuous routing structure for fast,
TM
pin-compatibility (with other FLEX
208-Pin
PQFP
171
171
171
240-Pin
PQFP
TM
199
199
packages (see
Table
256-Pin
BGA
204
218
2)
Table
Altera Corporation
®
FineLine BGA
6000 devices)
2)
256-pin
171
219