EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 129

IC STRATIX II GX 30K 780-FBGA

EP2SGX30CF780C4N

Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX30CF780C4N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX30CF780C4N
Manufacturer:
ALTERA
0
Figure 2–84. Stratix II GX IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
(3)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–84:
clkout
aclr/apreset
sclr/spreset
ce_out
oe
Chip-Wide Reset
Output Register
Output Register
OE Register
OE Register
ENA
CLRN/PRN
CLRN/PRN
CLRN/PRN
CLRN/PRN
D
ENA
D
ENA
D
ENA
D
Q
Q
Q
Q
Used for
DDR, DDR2
SDRAM
Notes
clk
Stratix II GX Device Handbook, Volume 1
Open-Drain Output
Drive Strength
Pin Delay
(1),
Output
Control
(2)
OE Register
t CO Delay
Stratix II GX Architecture
V CCIO
V CCIO
PCI Clamp (3)
Termination
On-Chip
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
2–121

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