EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 154
EP2SGX30CF780C4N
Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N
EP2SGX30CF780C4N
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Document Revision History
2–146
Stratix II GX Device Handbook, Volume 1
Table 2–42. Document Revision History (Part 4 of 6)
Document
Date and
Version
Updated:
●
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Updated bulleted lists at the beginning of the
“Transceivers” section.
Added reference to the “Transmit Buffer”
section.
Deleted the Programmable V
“Programmable Output Driver” section.
Data Width” heading in Table 2–14.
Deleted “Global & Regional Clock
Connections from Right Side Clock Pins &
Fast PLL Outputs” table.
Updated notes to Tables 2–29 and 2–37.
Updated notes to Figures 2–72, 2–73 and
2–74.
Updated bulleted list in the “Advanced I/O
Standard Support” section.
Changed “PLD Interface” heading to “Parallel
“Transmitter PLLs”
“Transmitter Phase Compensation FIFO
Buffer”
“8B/10B Encoder”
“Byte Serializer”
“Programmable Output Driver”
“Receiver PLL & CRU”
“Programmable Pre-Emphasis”
“Receiver Input Buffer”
“Control and Status Signals”
“Programmable Run Length Violation”
“Channel Aligner”
“Basic Mode”
“Byte Ordering Block”
“Receiver Phase Compensation FIFO
Buffer”
“Loopback Modes”
“Serial Loopback”
“Parallel Loopback”
“Regional Clock Network”
“MultiVolt I/O Interface”
“High-Speed Differential I/O with DPA
Support”
Changes Made
OD
table from the
Summary of Changes
Altera Corporation
October 2007
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