EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 15
EP2SGX30CF780C4N
Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N
EP2SGX30CF780C4N
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Altera Corporation
October 2007
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer resides in the
transceiver block at the PCS/FPGA boundary and cannot be bypassed.
This FIFO buffer compensates for phase differences between the
transmitter PLL clock and the clock from the PLD. After the transmitter
PLL has locked to the frequency and phase of the reference clock, the
transmitter FIFO buffer must be reset to initialize the read and write
pointers. After FIFO pointer initialization, the PLL must remain phase
locked to the reference clock.
Byte Serializer
The FPGA and transceiver block must maintain the same throughput. If
the FPGA interface cannot meet the timing margin to support the
throughput of the transceiver, the byte serializer is used on the
transmitter and the byte deserializer is used on the receiver.
The byte serializer takes words from the FPGA interface and converts
them into smaller words for use in the transceiver. The transmit data path
after the byte serializer is 8, 10, 16, or 20 bits. Refer to
transmitter data with the byte serializer enabled. The byte serializer can
be bypassed when the data width is 8, 10, 16, or 20 bits at the FPGA
interface.
If the byte serializer is disabled, the FPGA transmit data is passed without
data width conversion.
Table 2–3. Transmitter Data with the Byte Serializer Enabled
Input Data Width
16 bits
20 bits
32 bits
40 bits
Stratix II GX Device Handbook, Volume 1
Output Data Width
Stratix II GX Architecture
10 bits
16 bits
20 bits
8 bits
Table 2–3
for the
2–7
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