EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 104
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EP2S60F484I4N
Manufacturer Part Number
EP2S60F484I4N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1910
EP2S60F484I4N
EP2S60F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
NANYA
Quantity:
30
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
20 000
High-Speed Differential I/O with DPA Support
High-Speed
Differential I/O
with DPA
Support
2–96
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Non-Stratix II VCC = 3.3 V
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Device
The TDO output buffer meets V
The TDO output buffer meets V
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
Input buffer must be 3.3-V tolerant.
Input buffer must be 2.5-V tolerant.
Input buffer must be 1.8-V tolerant.
Table
2–20:
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
Buffer Power
TDI Input
Stratix II devices contain dedicated circuitry for supporting differential
standards at speeds up to 1 Gbps. The LVDS and HyperTransport
differential I/O standards are supported in the Stratix II device. In
addition, the LVPECL I/O standard is supported on input and output
clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high
speed I/O interconnect standards and applications:
■
■
■
■
There are four dedicated high-speed PLLs in the EP2S15 to EP2S30
devices and eight dedicated high-speed PLLs in the EP2S60 to EP2S180
devices to multiply reference clocks and drive high-speed differential
SERDES channels.
Tables 2–21
can clock in each of the Stratix II devices. In
first row for each transmitter or receiver provides the number of channels
driven directly by the PLL. The second row below it shows the maximum
channels a PLL can drive if cross bank channels are used from the
adjacent center PLL. For example, in the 484-pin FineLine BGA EP2S15
V
C C I O
v
v
v
OH
OH
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
Parallel RapidIO
HyperTransport technology
v
(1),
(1),
(1),
(MIN) = 2.4 V.
(MIN) = 2.0 V.
= 3.3 V V
(1)
(4)
(4)
(4)
through
Stratix II TDO V
C C I O
v
v
v
v
2–26
(2),
(2),
= 2.5 V V
(2)
(2)
(5)
(5)
show the number of channels that each fast PLL
C C I O
C C I O
Voltage Level in I/O Bank 4
v
v
v
v
= 1.8 V V
(3)
(3)
(6)
Tables 2–21
Level shifter
Level shifter
Level shifter
C C I O
required
required
required
v
= 1.5 V V
Altera Corporation
through
Level shifter
Level shifter
Level shifter
C C I O
required
required
required
May 2007
2–26
v
= 1.2 V
the