EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 150
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EP2S60F484I4N
Manufacturer Part Number
EP2S60F484I4N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1910
EP2S60F484I4N
EP2S60F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
NANYA
Quantity:
30
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
20 000
Operating Conditions
5–14
Stratix II Device Handbook, Volume 1
Note to
(1)
Note to
(1)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Table 5–23. 1.5-V HSTL Class I Specifications
Table 5–24. 1.5-V HSTL Class II Specifications
Symbol
Symbol
CCIO
REF
TT
IH
IL
IH
IL
OH
OL
CCIO
REF
TT
IH
IL
IH
IL
OH
OL
(DC)
(AC)
(DC)
(AC)
(DC)
(AC)
(DC)
(AC)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table
Table
Output supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
Output supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
5–23:
5–24:
Parameter
Parameter
I
I
I
I
OH
OH
OH
OH
Conditions
= 8 mA
= –8 mA
Conditions
= 16 mA
= –16 mA
(1)
(1)
(1)
(1)
V
V
V
V
V
V
Minimum
Minimum
CCIO
CCIO
REF
REF
REF
REF
1.425
0.713
0.713
1.425
0.713
0.713
–0.3
–0.3
+ 0.1
+ 0.2
+ 0.1
+ 0.2
– 0.4
– 0.4
Typical
Typical
1.500
0.750
0.750
1.500
0.750
0.750
Altera Corporation
V
V
Maximum
V
Maximum
V
REF
REF
REF
REF
1.575
0.788
0.788
1.575
0.788
0.788
0.4
0.4
– 0.1
– 0.2
– 0.1
– 0.2
April 2011
Unit
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V