EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 226
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EP2S60F484I4N
Manufacturer Part Number
EP2S60F484I4N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1910
EP2S60F484I4N
EP2S60F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
NANYA
Quantity:
30
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
20 000
High-Speed I/O Specifications
5–90
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
f
f
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
H S C L K
H S C L K
H S D R
H S D R D PA
DUTY
Table 5–91. High-Speed I/O Specifications for -5 Speed Grade
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
(clock frequency)
= f
R I S E
FA L L
Table
Symbol
H S D R
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
5–91:
/ W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential I/O standards
All differential I/O standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
SPI-4
Parallel Rapid I/O
Miscellaneous
Table 5–91
grade Stratix II devices.
Standard
shows the high-speed I/O timing specifications for -5 speed
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
Training
Pattern
Transition
Density
100%
10%
25%
50%
Notes
(1),
0.44
Min
150
150
256
256
256
256
256
150
440
16
16
(4)
(4)
45
-5 Speed Grade
-
(2)
Typ
50
Altera Corporation
6,400
Max
420
500
640
840
700
500
840
200
190
290
290
55
-
Number of
repetitions
April 2011
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
Unit
ps
ps
ps
ps
ps
UI
UI
%