EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 96

• Manufacturer Part Number: EP2S60F484I4N
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 334
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1910; EP2S60F484I4N

I/O Structure
Figure 2–57. Stratix II I/O Banks
Notes to
(1)
(2)
(3)
(4)
2–88
Stratix II Device Handbook, Volume 1
Figure 2–57
representation only.
Depending on the size of the device, different device members have different numbers of V
pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent V
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
Horizontal I/O banks feature SERDES and DPA circuitry for high speed differential I/O standards. See the High
Speed Differential I/O Interfaces in Stratix II & Stratix II GX Devices chapter of the Stratix II Device Handbook, Volume 2
or the Stratix II GX Device Handbook, Volume 2 for more information on differential I/O standards.
PLL7
PLL1
PLL2
PLL8
Figure
VREF0B3
VREF4B8
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
2–57:
DQS8T
DQS8B
is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
VREF1B3
VREF3B8
DQS7T
DQS7B
VREF2B3
Bank 3
Bank 8
VREF2B8
DQS6T
DQS6B
VREF3B3
VREF1B8
Notes
DQS5T
DQS5B
(1), (2), (3),
VREF4B3
VREF0B8
operations. HSTL-18 Class II, HSTL-15-Class II,
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
SSTL-18 Class II standards are only supported
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
Bank 11
Bank 12
PLL11
PLL12
for input operations.
(4)
Bank 10
Bank 9
PLL5
PLL6
VREF0B4
VREF4B7
DQS4T
DQS4B
VREF1B4
VREF3B7
DQS3B
DQS3T
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 4
Bank 7
VREF2B4
VREF2B7
DQS2T
DQS2B
VREF3B4
VREF1B7
DQS1T
DQS1B
REF
Altera Corporation
VREF4B4
VREF0B7
DQS0T
DQS0B
groups. Refer to the
PLL10
PLL4
PLL3
PLL9
May 2007
REF
group