XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 43

• Manufacturer Part Number: XC4005L-5PQ100C
• Description: IC 3.3V FPGA 196 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ100C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1121

Table 18: Pin Descriptions
September 18, 1996 (Version 1.04)
Permanently Dedicated Pins
User I/O Pins That Can Have Special Functions
M0, M1, M2
PROGRAM
RDY/BUSY
Pin Name
DONE
CCLK
RCLK
GND
VCC
Config.
During
I or O
I/O
I/O
O
O
I
I
I
I
Config.
O (M1),
I (M0),
I (M2)
After
I/O
I/O
I/O
O
I
I
I
I
Eight or more (depending on package) connections to the nominal +5 V supply voltage
(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 F capacitor to Ground.
Eight or more (depending on package type) connections to Ground. All must be con-
nected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and
can be selected as the Readback Clock. There is no CCLK High time restriction on
XC4000-Series devices, except during Readback. See
and Low Time Specification for the Readback Clock” on page 65
this exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of out-
puts.
The optional pull-up resistor is selected as an option in MakeBits, the XACT step pro-
gram that creates the configuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000EX) is preceded by a rising edge on RCLK, a redundant output signal. RCLK
is useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
During configuration, these pins have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 k is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
Pin Description
“Violating the Maximum High
for an explanation of
4-47