XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 39

• Manufacturer Part Number: XC4005L-5PQ100C
• Description: IC 3.3V FPGA 196 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ100C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1121

Global Nets and Buffers (XC4000EX only)
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to
the vertical longlines used for standard interconnect. The
global lines are broken in the center of the array, to allow
faster distribution and to minimize skew across the whole
array. Each half-column global line has its own buffered
multiplexer, as shown in
bal lines cannot be connected across the center of the
device, as this connection might introduce unacceptable
skew. The top and bottom halves of the global lines must
be separately driven — although they can be driven by the
same global buffer.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be
driven by internal logic, because they can be accessed by
single, double, and quad lines at the top, bottom, half, and
quarter points.
clocks that can be used simultaneously in an XC4000EX
device is very large.
There are four global lines feeding the IOBs at the left edge
of the device. IOBs along the right edge have eight global
lines. There is a single global line along the top and bottom
edges with access to the IOBs. All IOB global lines are bro-
ken at the center. They cannot be connected across the
center of the device, as this connection might introduce
unacceptable skew.
IOB global lines can be driven from any of three types of
global buffers, or from local interconnect. Alternatively, top
and bottom IOBs can be clocked from the global lines in the
adjacent CLB column.
Three different types of clock buffers are available in the
XC4000EX:
• Global Low-Skew Buffers (BUFGLS)
• Global Early Buffers (BUFGE)
• FastCLK Buffers (BUFFCLK)
Global Low-Skew Buffers are the standard clock buffers.
They should be used for most internal clocking, whenever a
large portion of the device must be driven.
Global Early Buffers are designed to provide a faster clock
access, but CLB access is limited to one-fourth of the
device. They also facilitate a faster I/O interface.
FastCLK buffers are specifically designed to provide the
fastest possible I/O clock. They have only the standard
input access to CLBs, through local interconnect.
Figure 36
ture in the XC4000EX.
Global Early buffers and Global Low-Skew buffers share a
single pad. Therefore, the same IPAD symbol can drive
one buffer of each type, in parallel. This configuration is
particularly useful when using the Fast Capture latches, as
described in
September 18, 1996 (Version 1.04)
is a conceptual diagram of the global net struc-
“IOB Input Signals” on page
Consequently, the number of different
Figure
36. The top and bottom glo-
24. Paired Global
Early and Global Low-Skew buffers share a common input;
they cannot be driven by two different signals.
Choosing an XC4000EX Clock Buffer
The clocking structure of the XC4000EX provides a large
variety of features. However, it can be simple to use, with-
out understanding all the details. The software automati-
cally handles clocks, along with all other routing, when the
appropriate clock buffer is placed in the design. In fact, if a
buffer symbol called BUFG is placed, rather than a specific
type of buffer, the software even chooses the buffer most
appropriate for the design. The detailed information in this
section is provided for those users who want a finer level of
control over their designs.
If fine control is desired, use the following summary and
Table 17 on page 41
• The simplest thing to do is to use a Global Low-Skew
• If a faster clock path is needed, try a BUFG. The
• If a single quadrant of the chip is sufficient for the
• In special cases, where both external and internal
Global Low-Skew Buffers
Each corner of the XC4000EX device has two Global Low-
Skew buffers. Any of the eight Global Low-Skew buffers
can drive any of the eight vertical Global lines in a column
of CLBs. In addition, any of the buffers can drive any of the
four vertical lines accessing the IOBs on the left edge of the
device, and any of the eight vertical lines accessing the
IOBs on the right edge of the device. (See
page
IOBs at the top and bottom edges of the device are
accessed through the vertical Global lines in the CLB array,
as in the XC4000E. Any Global Low-Skew buffer can,
therefore, access every IOB and CLB in the device.
The Global Low-Skew buffers can be driven by either semi-
dedicated pads or internal logic.
To use a Global Low-Skew buffer, place a BUFGLS ele-
ment in a schematic or in HDL code. If desired, attach a
LOC attribute or property to direct placement to the desig-
nated location. For example, attach a LOC=T attribute or
property to direct that a BUFGLS be placed in one of the
two Global Low-Skew buffers on the top edge of the device,
or a LOC=TR to indicate the Global Low-Skew buffer on the
top edge of the device, on the right.
buffer.
software will first try to use a Global Low-Skew Buffer. If
timing requirements are not met, a faster buffer will
automatically be used.
clocked logic, and the timing requires a faster clock than
the Global Low-Skew buffer, use a Global Early buffer.
timing have been carefully studied, a FastCLK buffer
can be used, for the fastest possible I/O clock path.
44.)
to choose an appropriate clock buffer.
Figure 37 on
4-43