XC4VLX40-10FFG1148C Xilinx Inc, XC4VLX40-10FFG1148C Datasheet - Page 17
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XC4VLX40-10FFG1148C
Manufacturer Part Number
XC4VLX40-10FFG1148C
Description
IC FPGA VIRTEX-4 40K 1148-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FFG1148C
Total Ram Bits
1769472
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Number Of I /o
640
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1148-BBGA, FCBGA
No. Of Logic Blocks
4608
No. Of Macrocells
41472
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
640
Clock Management
DCM
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1491
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX
Quantity:
1 238
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 25: RocketIO Receiver Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
Serial data rate, -10
Serial data rate, -11
XAUI Receive Jitter Tolerance (8B/10B CJPAT)
General Receive Jitter Tolerance
RXUSRCLK frequency
RXUSRCLK2 frequency
RXUSRCLK duty cycle
RXUSRCLK2 duty cycle
Differential input skew
Differential receive input sensitivity
On-chip AC coupling corner frequency
Signal detect response time
Input capacitance at the Die
Excess capacitance at the solder ball
Receive Deterministic Jitter Tolerance
Receive Total Jitter Tolerance
Receive Sinusoidal Jitter Tolerance
Receive deterministic jitter tolerance
Sinusoidal jitter tolerance
UI = Unit Interval
Using receiver equalization setting of 111 (14 dB).
ACDR = Analog CDR and DCDR = Digital CDR.
Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency
sinusoidal jitter (SJ).
Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ +
0.15 UI of RJ.
Description
(2)
RXSIGDET
T
T
T
Symbol
DJTOL
T
T
T
T
SJTOL
T
TJTOL
C
F
F
V
T
RX2DC
ISKEW
C
DJTOL
SJTOL
T
RXDC
BALL
GRX
GRX
RX2
EYE
DIE
RX
(2)
(2,4)
(6)
(7)
Responsetime
Rate (Gb/s) Mode
Rate (Gb/s)
For slower speed grades = MaxDataRate/32
3.125
0.622
4.25
4.25
1.25
1.25
1.25
www.xilinx.com
3.125
3.125
3.125
3.125
3.125
3.125
0.622
6.5
5.0
6.5
5.0
2.5
1.25
1.25
1.25
2.5
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(5)
(5)
(9)
(9)
(8)
(5)
(9)
(8)
(8)
(8)
(8)
(8)
6.
7.
8.
9.
Conditions
Mode
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
DCDR
DCDR
DCDR
ACDR
ACDR
ACDR
ACDR
ACDR
ACDR
DCDR
DCDR
DCDR
Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter
as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5.
SJ in addition to 0.55 UI of DJ +RJ.
Jitter frequency = 5 MHz.
Jitter frequency = 10 MHz.
(3)
(3)
Frequency
f = 22.1 kHz
f = 1.875 MHz
f = 20 MHz
PRBS31
PRBS31
PRBS31
PRBS31
Pattern
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
PRBS7
0.622
0.622
Min
110
40
40
Typ
30
3.125
0.37
0.65
0.10
0.10
0.65
0.65
0.65
0.60
0.55
0.50
0.50
0.40
0.40
0.65
0.65
0.65
0.50
0.50
0.50
0.55
0.35
0.55
Max
250
250
6.5
8.5
60
60
20
Units
Gb/s
Gb/s
UI
UI
MHz
MHz
mV
ps
ns
%
%
fF
fF
(1)
(1)
17