XC4VLX40-10FFG1148C Xilinx Inc, XC4VLX40-10FFG1148C Datasheet - Page 29
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XC4VLX40-10FFG1148C
Manufacturer Part Number
XC4VLX40-10FFG1148C
Description
IC FPGA VIRTEX-4 40K 1148-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FFG1148C
Total Ram Bits
1769472
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Number Of I /o
640
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1148-BBGA, FCBGA
No. Of Logic Blocks
4608
No. Of Macrocells
41472
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
640
Clock Management
DCM
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1491
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX
Quantity:
1 238
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
IDELAYCTRL
T
F
IDELAYCTRL_REF_PRECISION
T
IDELAY
T
T
T
F
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYRESOLUTION
IDELAYTOTAL_ERR
IDELAYPAT_JIT
MAX
Refer to Xilinx Application Note
See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the
This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
Units in ps peak-to-peak per tap.
Symbol
(2)
XAPP707
Reset to Ready for IDELAYCTRL
(Maximum)
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
IDELAY Chain Delay Resolution
Cumulative delay at a given tap
Pattern dependent period jitter in delay
chain for clock pattern
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
C clock maximum frequency
for details on IDELAY timing characteristics.
Description
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(3)
Virtex-4 FPGA User
10 ± 2
3.00
50.0
-12
200
±10
300
75
0
± 0.07[(tap −1) x 75 +34]
[(tap −1) x 75 +34]
Guide: Chapter 7, SelectIO Logic Resources.
Speed Grade
10 ± 2
3.00
50.0
-11
200
±10
250
75
0
10 ± 2
3.00
50.0
-10
200
±10
250
75
0
Note (4)
Note (4)
Units
MHz
MHz
MHz
µs
ns
ps
ps
29