XC4VLX40-10FFG1148C Xilinx Inc, XC4VLX40-10FFG1148C Datasheet - Page 23
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XC4VLX40-10FFG1148C
Manufacturer Part Number
XC4VLX40-10FFG1148C
Description
IC FPGA VIRTEX-4 40K 1148-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FFG1148C
Total Ram Bits
1769472
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Number Of I /o
640
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1148-BBGA, FCBGA
No. Of Logic Blocks
4608
No. Of Macrocells
41472
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
640
Clock Management
DCM
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1491
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX
Quantity:
1 238
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30
Table 30: Input Delay Measurement Methodology
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface),
33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL, Class III & IV
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
ULVDS (Ultra LVDS), 2.5V
LDT (HyperTransport), 2.5V
Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage.
Parameters for all other DCI standards are the same as for the corresponding non-DCI standards.
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the V
shows the test setup parameters used for measuring input delay.
Description
L
and V
H
.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCIX
GTL
GTLP
HSTL_I, HSTL_II
HSTL_III, HSTL_IV
HSTL_I_18, HSTL_II_18
HSTL_III_18,
HSTL_IV_18
SSTL3_I, SSTL3_II
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
AGP
LVDS_25
LVDSEXT_25
ULVDS_25
LDT_25
www.xilinx.com
REF
I
REF
/O Standard
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Attribute
values. Reported delays reflect worst case of these measurements. V
/ V
MEAS
parameters found in IBIS models and/or noted in
V
V
(0.2 xV
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
V
V
L
REF
0
0
0
(1,2)
0
0
– 1.00
– 0.75
Per PCI-X™ Specification
– 0.2
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
CCO
Per PCI™ Specification
–
Per PCI Specification
)
V
V
(0.2 xV
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
V
V
H
REF
3.0
3.3
2.5
1.8
1.5
(1,2)
+ 1.00
+ 0.75
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
CCO
+
)
V
Figure
(1,4,5)
V
V
V
V
V
V
V
V
V
V
1.25
0.75
MEAS
1.65
1.4
1.2
1.2
0.6
0.6
0.9
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
4.
REF
V
(1,3,5)
Spec
AGP
0.80
0.75
0.90
0.90
1.08
1.25
0.90
1.0
1.5
values
REF
–
–
–
–
–
–
–
–
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