XC4VLX40-10FFG1148C Xilinx Inc, XC4VLX40-10FFG1148C Datasheet - Page 54
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XC4VLX40-10FFG1148C
Manufacturer Part Number
XC4VLX40-10FFG1148C
Description
IC FPGA VIRTEX-4 40K 1148-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FFG1148C
Total Ram Bits
1769472
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Number Of I /o
640
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1148-BBGA, FCBGA
No. Of Logic Blocks
4608
No. Of Macrocells
41472
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
640
Clock Management
DCM
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1491
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX
Quantity:
1 238
Company:
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VLX40-10FFG1148C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS302 (v3.7) September 9, 2009
Product Specification
02/03/06
03/22/06
06/01/06
06/23/06
08/23/06
Date
Version
1.14.1
1.11
1.12
1.13
1.15
Revised the speed specification requirements in
parameter changes in
and I
Table
Table
600 mV and added a new Note 1. Also in
specification from 95mV to 950mV. Changed performance numbers in
the typical specification for T
maximum to
Table
CLKIN_FREQ_PMCD_CLKA_MAX -12 specification in
T
Stepping
Modified second paragraph in
numbers for I
typ value of the DC Parameter, Common Mode Input Voltage Range from 600 MV to
800 MV in
(V
(R
to
Table
Changed
grade from
changed the -12 and -11 speed grade to 6.5 Gb/s, and deleted Note 1 in
Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Reference
Clock total jitter, peak-peak (T
data rate F
2.5 Gb/s to 6.5 Gb/s for Serial data output deterministic jitter (T
condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output
random jitter (T
Virtex-4 FPGA Electrical Characteristics, page
the -11x for XC4VFX devices.
I
for values I
page
designations for the XC4VFX devices.
characteristics:
page
and units. Updated notes.
1. Note 2 is now Note 1, and the reference has also been changed.
removed Input Signal Requirements.
page
Table 24, page
65 ps Typ to 400 ps Max.
-11, and -10 Speed Grades for T
T
the speeds specification for -12 Speed Grades, Sequential Delay characteristics: T
T
Virtex-4 FX devices.
CCCAUXMGT
BUFIO_MAX_FREQ
IDELAYRESOLUTION_ERR
REGXB
ICMC
IN
Table
). Changed the SPI4.2 entry for -11 from 900 Mb/s to 1 Gb/s in
RPD
11: changed DC parameters and values and added note.
18,
46,
7. Inserted notes into
12, revised Common Mode Input Voltage Range (V
43. Added note 5 to
26). Added Note 5 to
), Peak-to-Peak Differential Input Voltage (V
, T
15. Reduced the maximum frequency from 322 MHz to 250 MHz (in
specifications in
for most characteristics:
Table 57, page
V
and
REGYB
Table
GTX
CCAUXRX
IN
Table
, I
T
CCINTMIN
and
TTX
IDELAYCTRLCO_RDY
Current Virtex-4 Production Devices
to 6.5 Gb/s. Deleted first condition and changed second condition to
RJ
16: changed value for Reference Clock Rise/Fall Time (T
changed conditions, speed grade (typ and max) values, and units.
12. Added three DC parameters to
, T
, I
14. Updated to speed specification v1.60. Removed -11X speed grade,
), both in
V
specification in
TS
CKSH
TRX
, I
CCAUXTX
values and added notes to
, I
Table 54
, and new notes 2 and 3.
www.xilinx.com
CCAUXMIN
, and T
47, and
and added row for T
Table
Table 35, page
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 43, page
Table
Table 26, page
Table
Table
DJ
GJTT
Power-On Power Supply
Table 3, page
, and a new parameter
, I
from
3. Changed LVCMOS18 to meet the JEDEC specification in
REGF5
and
TTX
45. Revised notes 3 and 5 in
Table 58, page
IDELAYRESOLUTION
8,
, and I
40.
Table
changed conditions, speed grade (typ and max) values,
) in
Table
Table
Table
, I
Table 54, page
.
Table 24, page
TRX
Table 24, page 16
Table 65, page
Revisions
CCOMIN,
59. Changed the information in the
29: changed the speeds specification for the -12,
36:
Table
26. Added note 2 to
,I
9, and
56. Added Note 7 to
18.
AUMGT
3: added new values for I
IDELAYTOTAL_ERR
removed the Tcnfig symbol, values, and note
12, changed Common Mode Voltage
Switching Characteristics, page
and added Note 2
48: corrected large speed numbers to N/A.
Table 4, page
Table
Table 1, page
1: removed paragraph on that introduced
and new notes 4 and 5.
IDIFF
Table
, deleted row for
44,
16. Changed the max value for Serial
T
52: added stepping information for
sections.
10. Corrected note 1 in
IDELAYPAT_JIT
), and Differential Input Resistance
Table
Table 55, page
Requirements. Added/Changed
12, Input Common-Mode Voltage
ICM
and
) typical from 800 mV to
.
53. Changed the
Table 25, page 17, for most
Table
Table
Table 39, page
4: added new symbols and
Table
DJ
1. Removed -11X speed
Table
) and deleted first
. Revised Note 1 in
Table
(Table
50. Changed the
27. In
Table 50, page
2. Added to the I
14: changed speed
CCAUXRX
Table
Table 23, page
RCLK
45,
13. Added Note 3
5). Changed the
Table
Table 12,
Production
Table 56,
23. Removed
; T
Table 25
32: changed
Table
, I
FCLK
35, added
CCAUXTX
Table 26,
12, with
REG
42:
) from
11. In
RPU
and
16.
,
,
54