EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 103

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Table 5–12. Dynamic Phase Shifting Control Signals
© December 2010 Altera Corporation
phasecounterselect[2..0]
phaseupdown
phasestep
scanclk
phasedone
Signal Name
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust t
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
Table 5–12
Table 5–13
PHASECOUNTERSELECT setting.
Table 5–13. Phase Counter Select Mapping
[2]
0
0
0
0
1
1
1
lists the control signals that are used for dynamic phase shifting.
lists the PLL counter selection based on the corresponding
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to select
all C counters. This signal is registered in the
PLL on the rising edge of scanclk.
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
the rising edge of scanclk.
Logic high enables dynamic phase shifting.
Free running clock from core used in
combination with phasestep to enable or
disable dynamic phase shifting. Shared with
scanclk for dynamic reconfiguration.
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
De
phasecounterselect
- asserts on the rising edge of scanclk.
[1]
0
0
1
1
0
0
1
Description
[0]
0
1
0
1
0
1
0
Logic array or I/O
pins
Logic array or I/O
pins
Logic array or I/O
pins
GCLK or I/O pins
PLL reconfiguration
circuit
Cyclone IV Device Handbook, Volume 1
All Output Counters
Source
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
M Counter
Selects
CO
delays by
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
Logic array or
I/O pins
Destination
5–41