EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 174

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–8
Configuration Scheme
Table 8–3. Configuration Schemes for Cyclone IV GX Devices (EP4CGX15, EP4CGX22, and EP4CGX30 [except for F484
Package])
Table 8–4. Configuration Schemes for Cyclone IV GX Devices (EP4CGX30 [only for F484 package], EP4CGX50, EP4CGX75,
EP4CGX110, and EP4CGX150) (Part 1 of 2)
Cyclone IV Device Handbook, Volume 1
Notes to
(1) Configuration voltage standard applied to the V
(2) JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored.
(3) Do not leave the MSEL pins floating. Connect them to V
JTAG-based configuration
Configuration Scheme
Altera recommends connecting the MSEL pins to GND if your device is only using JTAG configuration.
Configuration Scheme
Table
FPP
AS
PS
8–3:
AS
PS
1
A configuration scheme with different configuration voltage standards is selected by
driving the MSEL pins either high or low, as shown in
Table
Hardwire the MSEL pins to V
avoid problems detecting an incorrect configuration scheme. Do not drive the MSEL
pins with a microprocessor or another device.
(2)
8–5.
MSEL3 MSEL2 MSEL1 MSEL0
1
1
1
1
1
1
1
0
0
0
0
0
MSEL2
(3)
1
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
1
0
0
CCIO
MSEL1
supply of the bank in which the configuration pins reside.
(3)
0
1
0
1
0
1
0
CCA
0
1
0
1
0
1
0
0
1
0
0
1
or GND. These pins support the non-JTAG configuration scheme used in production.
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
CCA
MSEL0
(3)
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
or GND without pull-up or pull-down resistors to
POR Delay
POR Delay
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
—
Configuration Voltage Standard (V)
Configuration Voltage Standard (V)
Table
© December 2010 Altera Corporation
8–3,
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.0, 2.5
3.0, 2.5
1.8, 1.5
Table
3.0, 2.5
3.0, 2.5
1.8, 1.5
1.8, 1.5
1.8, 1.5
1.8, 1.5
3.3
3.3
—
3.3
3.3
8–4, and
Configuration
(1)
(1)