EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 285

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel Datapath
8B/10B Encoder
© December 2010 Altera Corporation
f
f
1
For the FPGA fabric-transceiver interface frequency specifications, refer to the
IV Device Data
For example, when operating an EP4CGX150 transmitter channel at 3.125 Gbps
without byte serializer, the FPGA fabric frequency is 312.5 MHz (3.125 Gbps/10). This
implementation violates the frequency limit and is not supported. Channel operation
at 3.125 Gbps is supported when byte serializer is used, where the FPGA fabric
frequency is 156.25 MHz (3.125 Gbps/20).
The byte serializer forwards the least significant byte first, followed by the most
significant byte.
The optional 8B/10B encoder generates 10-bit code groups with proper disparity from
the 8-bit data and 1-bit control identifier as shown in
The encoder is compliant with Clause 36 of the
Figure 1–5. 8B/10B Encoder Block Diagram
The 1-bit control identifier (tx_ctrlenable) port controls the 8-bit translation to
either a 10-bit data word (Dx.y) or a 10-bit control word (Kx.y).
8B/10B encoding operation with the tx_ctrlenable port, where the second 8'hBC
data is encoded as a control word when tx_ctrlenable port is asserted, while the
rest of the data is encoded as a data word.
Figure 1–6. Control and Data Word Encoding with the 8B/10B Encoder
The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters
for which the tx_ctrlenable port should be asserted. If you assert
tx_ctrlenable port for any other set of characters, the 8B/10B encoder might
encode the output 10-bit code as an invalid code (it does not map to a valid Dx.y or
Kx.y code), or an unintended valid Dx.y code, depending on the value entered. It is
possible for a downstream 8B/10B decoder to decode an invalid control word into a
valid Dx.y code without asserting any code error flags. Altera recommends not to
assert tx_ctrlenable port for unsupported 8-bit characters.
tx_datain[7..0]
tx_ctrlenable
code group
Sheet.
clock
D3.4
83
tx_ctrlenable
tx_forcedisp
tx_dispval
D24.3
78
8
D28.5
BC
8B/10B Encoder
K28.5
BC
IEEE 802.3
D15.0
0F
Figure
10
D0.0
00
Cyclone IV Device Handbook, Volume 2
Specification.
1–5.
D31.5
Figure 1–6
BF
D28.1
3C
shows the
Cyclone
1–5