EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 105

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EP4CE55F23C7

Manufacturer Part Number
EP4CE55F23C7
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE55F23C7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Spread-Spectrum Clocking
Spread-Spectrum Clocking
PLL Specifications
Document Revision History
Table 5–14. Document Revision History
© December 2010 Altera Corporation
December 2010
July 2010
February 2010
November 2009
Date
f
Cyclone IV devices can accept a spread-spectrum input with typical modulation
frequencies. However, the device cannot automatically detect that the input is a
spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the
input of the PLL. PLLs of Cyclone IV devices can track a spread-spectrum input clock
as long as it is in the input jitter tolerance specifications and the modulation frequency
of the input clock is below the PLL bandwidth, that is specified in the fitter report.
Cyclone IV devices cannot generate spread-spectrum signals internally.
For information about PLL specifications, refer to the
chapter.
Table 5–14
Version
2.2
2.1
2.0
1.0
lists the revision history for this chapter.
Initial release.
Updated for the Quartus II software version 10.1 release.
Updated
Updated
and
Minor text edits.
Updated Figure 5–2, Figure 5–3, Figure 5–4, and Figure 5–10.
Updated Table 5–1, Table 5–2, and Table 5–5.
Updated “Clock Feedback Modes” section.
Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1
release.
Updated “Clock Networks” section.
Updated Table 5–1 and Table 5–2.
Added Table 5–3.
Updated Figure 5–2, Figure 5–3, and Figure 5–9.
Added Figure 5–4 and Figure 5–10.
“Manual Override”
Figure 5–3
“GCLK Network Clock Source
and
sections.
Figure
5–10.
Changes Made
Generation”,
Cyclone IV Device Datasheet
Cyclone IV Device Handbook, Volume 1
“PLLs in Cyclone IV
Devices”,
5–43

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