EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 85

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
No Compensation Mode
© December 2010 Altera Corporation
In no compensation mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because clock feedback into the PFD does not pass
through as much circuitry. Both the PLL internal and external clock outputs are phase
shifted with respect to the PLL clock input.
Figure 5–13
this mode.
Figure 5–13. Phase Relationship Between PLL Clocks in No Compensation Mode
Notes to
(1) Internal clocks fed by the PLL are phase
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Figure
shows a waveform example of the phase relationship of the PLL clock in
5–13:
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1), (2)
External PLL Clock
Outputs
(2)
Phase Aligned
-
aligned to each other.
Cyclone IV Device Handbook, Volume 1
5–23