EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 114

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

PLLs & Clock Networks
Figure 2–57. extclkena Signals
2–100
Stratix Device Handbook, Volume 1
COUNTER
OUTPUT
CLKENA
CLKOUT
resynchronization or relock period. The clkena signal can also disable
clock outputs if the system is not tolerant to frequency overshoot during
resynchronization.
The extclkena signals work in the same way as the clkena signals, but
they control the external clock output counters (e0, e1, e2, and e3). Upon
re-enabling, the PLL does not need a resynchronization or relock period
unless the PLL is using external feedback mode. In order to lock in
external feedback mode, the external output must drive the board trace
back to the FBIN pin.
Fast PLLs
Stratix devices contain up to eight fast PLLs with high-speed serial
interfacing ability, along with general-purpose features.
shows a diagram of the fast PLL.
Altera Corporation
Figure 2–58
July 2005