EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 264

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

PLL Specifications
PLL
Specifications
4–94
Stratix Device Handbook, Volume 1
f
f
f
f
t
t
t
f
f
t
t
t
t
t
t
t
f
t
IN
INPFD
INDUTY
EINDUTY
INJITTER
EINJITTER
FCOMP
OUT
OUT_EXT
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
LSKEW
Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2)
Symbol
Input clock frequency
Input frequency to PFD
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock
compensation time
Output frequency for internal global
or regional clock
Output frequency for external clock
(3)
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
Time required to reconfigure the
scan chains for PLLs 5 and 6
Time required to reconfigure the
scan chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale
counters/delays)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Clock skew between two external
clock outputs driven by the same
counter
Tables 4–127
specifications.
Parameter
(7)
(4)
(5)
through
4–129
(1),
Min
300
0.3
0.3
40
40
45
10
3
3
(2)
describe the Stratix device enhanced PLL
±50
Typ
±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk
289/f
193/f
±200
±200
800
Max
684
420
500
526
100
400
60
60
55
SCANCLK
SCANCLK
22
6
(8)
(3)
(3)
Altera Corporation
January 2006
ps or
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mUI
ps
ps
ns
μs
μs
ps
%
%
%