EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 230

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Timing Model
4–60
Stratix Device Handbook, Volume 1
Skew on Input Pins
Table 4–99
worst case I/O skew value. You can use these values, for example, when
calculating the timing budget on the input (read) side of a memory
interface.
PLL Counter & Clock Network Skews
Table 4–100
the Stratix device PLL.
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination and loading for each I/O standard. The timing
information is specified from the input clock pin up to the output pin of
Note to
(1)
Pins in the same I/O bank
Pins in top/bottom (vertical I/O) banks
Pins in left/right side (horizontal I/O) banks
Pins across the entire device
Clock skew between two external clock outputs driven
by the same counter
Clock skew between two external clock outputs driven
by the different counters with the same settings
Dual-purpose PLL dedicated clock output used as I/O
pin vs. regular I/O pin
Clock skew between any two outputs of the PLL that
drive global clock networks
Table 4–99. Package Skew on Input Pins
Table 4–100. PLL Counter & Clock Network Skews
The Quartus II software models 270 ps of delay on the PLL dedicated clock
output (PLL6_OUT[3..0]p/n and PLL5_OUT[3..0]p/n) pins both when
used as clocks and when used as I/O pins.
Table
shows the package skews that were considered to get the
shows the clock skews between different clock outputs from
4–100:
Package Parameter
Parameter
Worst-Case Skew (ps)
Worst-Case Skew (ps)
Altera Corporation
270
100
50
50
50
100
150
150
January 2006
(1)