EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 193

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
January 2006
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SU
H
CO
INREG2PIPE9
INREG2PIPE18
PIPE2OUTREG2ADD
PIPE2OUTREG4ADD
PD9
PD18
PD36
CLR
CLKHL
Table 4–39. DSP Block Internal Timing Microparameter Descriptions
Symbol
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
Input Register to DSP Block pipeline register in 9 × 9-bit
mode
Input Register to DSP Block pipeline register in 18 × 18-bit
mode
DSP Block Pipeline Register to output register delay in Two-
Multipliers Adder mode
DSP Block Pipeline Register to output register delay in Four-
Multipliers Adder mode
Combinatorial input to output delay for 9 × 9
Combinatorial input to output delay for 18 × 18
Combinatorial input to output delay for 36 × 36
Minimum clear pulse width
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in
reported by the timing analyzer in the Quartus II software.
Stratix Device Handbook, Volume 1
Parameter
Table 4–36 on page 4–20
DC & Switching Characteristics
and as
4–23