EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 192
![IC STRATIX FPGA 20K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S20F672I7
Manufacturer Part Number
EP1S20F672I7
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F672I7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
Quantity:
212
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Timing Model
4–22
Stratix Device Handbook, Volume 1
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
Stratix device internal timing microparameters for LEs, IOEs, TriMatrix
memory structures, DSP blocks, and MultiTrack interconnects.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
H
CO
LUT
CLR
PRE
CLKHL
SU_R
SU_C
H
CO_R
C O _ C
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKHL
Table 4–37. LE Internal Timing Microparameter Descriptions
Table 4–38. IOE Internal Timing Microparameter Descriptions
Symbol
Symbol
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
Minimum preset pulse width
Register minimum clock high or low time. The maximum core
clock frequency can be calculated by 1/(2 × t
Row IOE input register setup time
Column IOE input register setup time
IOE input and output register hold time after clock
Row IOE input and output register clock-to-output delay
Column IOE input and output register clock-to-output delay
Row input pin to IOE combinatorial output
Column input pin to IOE combinatorial output
Row IOE data input to combinatorial output pin
Column IOE data input to combinatorial output pin
Minimum clear pulse width
Minimum preset pulse width
Register minimum clock high or low time. The maximum I/O
clock frequency can be calculated by 1/(2 × t
Performance may also be affected by I/O timing, use of PLL,
and I/O programmable settings.
Tables 4–37
Parameter
Parameter
through
4–42
Altera Corporation
describe the
CLKHL
CLKHL
January 2006
).
).
™
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