EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 118

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–26
Arria II GX Device Handbook, Volume 1
1
Automatic Clock Switchover Mode
Use the switchover circuitry to automatically switch between inclk0 and inclk1
when the current reference clock to the PLL stops toggling. For example, in
applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (clksw) that controls the
multiplexer select input, as shown in
reference clock for the PLL. When you use the automatic switchover mode, you can
switch back and forth between the inclk0 and inclk1 clocks any number of times,
when one of the two clocks fails and the other clock is available.
When you use the automatic clock switchover mode, the following requirements
must be satisfied:
■
■
If the current clock input stops toggling while the other clock is also not toggling,
switchover is not initiated and the clkbad[0:1] signals are not valid. Also, if both
clock inputs are not the same frequency, but their period difference is 100%, the clock
sense block detects when a clock stops toggling, but the PLL may lose lock after the
switchover is completed and requires time to relock.
Altera recommends resetting the PLL with the areset signal to maintain the phase
relationships between the PLL input and output clocks when you use clock
switchover.
When you use automatic switchover mode, the clkbad[0] and clkbad[1] signals
indicate the status of the two clock inputs. When they are asserted, the clock sense
block has detected that the corresponding clock input has stopped toggling. These
two signals are not valid if the frequency difference between inclk0 and inclk1 is
greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or
inclk1) is being selected as the reference clock to the PLL. When the frequency
difference between the two clock inputs is more than 20%, the activeclock signal is
the only valid status signal.
Figure 5–20
switchover mode. In this example, the inclk0 signal is stuck low. After the inclk0
signal is stuck at low for approximately two clock cycles, the clock sense circuitry
drives the clkbad[0] signal high. Also, because the reference clock signal is not
toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to the backup clock, inclk1.
Both clock inputs must be running.
The period of the two clock inputs can differ by no more than 100% (2×).
shows an example waveform of the switchover feature with automatic
Figure
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
5–19. In this case, inclk1 becomes the
© July 2010 Altera Corporation
PLLs in Arria II GX Devices