EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 237

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Active Serial Configuration (Serial Configuration Devices)
Figure 9–7. Multi-Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to
(3) Connect the repeater buffers between the Arria II GX master and slave devices for DATA[0] and DCLK. This is to prevent any potential signal
(4) Arria II GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
© July 2010
integrity and clock skew problems.
Serial Configuration
Figure
Device
Altera Corporation
9–7:
1
DATA
DCLK
ASDI
nCS
Figure 9–7
As shown in
connected together with external pull-up resistors. These pins are open-drain
bidirectional pins on the devices. When the first device asserts nCEO (after receiving
all its configuration data), it releases its CONF_DONE pin. But the subsequent devices
in the chain keep this shared CONF_DONE line low until they have received their
configuration data. When all target devices in the chain have received their
configuration data and have released CONF_DONE, the pull-up resistor drives a high
level on this line and all devices simultaneously enter initialization mode.
While you can cascade Arria II GX devices, you cannot cascade or chain together
serial configuration devices.
If the configuration bitstream size exceeds the capacity of a serial configuration
device, you must select a larger configuration device and/or enable the compression
feature. When configuring multiple devices, the size of the bitstream is the sum of the
configuration bitstreams of the individual devices.
V
CCIO (1)
10 kΩ
Buffers (3)
V
CCIO
CCIO (1)
shows the pin connections for the multi-device AS configuration.
power supply of the I/O bank 3C.
10 kΩ
Figure
GND
V
CCIO (1)
9–7, the nSTATUS and CONF_DONE pins on all target devices are
10 kΩ
Arria II GX Device Master
DATA[0]
DCLK
nCSO
ASDO
nSTATUS
CONF_DONE
nCONFIG
nCE
CLKUSR
MSEL [3..0]
nCEO
(4)
(2)
V
CCIO (1)
10 kΩ
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
Arria II GX Device Slave
Arria II GX Device Handbook, Volume 1
MSEL [3..0]
nCEO
Table
9–2.
(2)
N.C.
9–17