EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 259

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Device Configuration Pins
Table 9–11. Dedicated Configuration Pins on the Arria II GX Device (Part 4 of 4)
Table 9–12. Optional Configuration Pins (Part 1 of 2)
© July 2010
DATA0
DATA[7..1]
Note to
(1) To tri-state AS configuration pins in the user mode, turn on the Enable input tri-state on active configuration pins in user mode option from
CLKUSR
INIT_DONE
Pin Name
the Device and Pin Options dialog box in the Configuration tab. This tri-states DCLK, DATA0, nCSO, and ASDO pins.
Pin Name
Table
(1)
Altera Corporation
9–11:
User Mode
N/A
N/A if option is on.
N/A if option is on.
I/O
I/O if option is off.
I/O if option is off.
Table 9–12
are not enabled in the Quartus II software, they are available as general-purpose user
I/O pins. Therefore, during configuration, these pins function as user I/O pins and
are tri-stated with weak pull-up resistors.
User Mode
Configuration
configuration
PS, FPP, AS
schemes
Scheme
Parallel
(FPP)
lists the optional configuration pins. If these optional configuration pins
open-drain
Pin Type
Output
Input
Pin Type
Inputs
Input
Optional user-supplied clock input synchronizes the
initialization of one or more devices. Enable this pin by turning
on the Enable user-supplied start-up clock (CLKUSR) option
in the Quartus II software.
Use as Status pin to indicate when the device has initialized
and is in user mode. When nCONFIG is low and during the
beginning of configuration, the INIT_DONE pin is tri-stated
and pulled high due to an external 10-k pull-up resistor.
After the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data),
the INIT_DONE pin goes low. When initialization is
complete, the INIT_DONE pin is released and pulled high
and the device enters user mode. Thus, the monitoring
circuitry must be able to detect a low-to-high transition. This
pin is enabled by turning on the Enable INIT_DONE output
option in the Quartus II software.
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on the
DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor that is
always active.
The DATA[0] is a dedicated pin that is used for both passive
and active configuration modes and it is not available as a
user I/O pin after configuration.
Data inputs. Byte-wide configuration data is presented to the
target device on DATA[7..0].
In serial configuration schemes, they function as user I/O pins
during configuration, which means they are tri-stated.
After FPP configuration, DATA[7..1] are available as user
I/O pins and the state of these pin depends on the
Dual-Purpose Pin settings.
Description
Description
Arria II GX Device Handbook, Volume 1
9–39