EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 174
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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6–2
I/O Standards Support
Stratix IV Device Handbook Volume 1
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This chapter contains the following sections:
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Stratix IV devices support a wide range of industry I/O standards.
I/O standards Stratix IV devices support, as well as the typical applications. These
devices support V
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2)
3.3-V LVTTL/LVCMOS (1),
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI/PCI-X
SSTL-2 Class I and II
SSTL-18 Class I and II
SSTL-15 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II
Differential SSTL-2 Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-15 Class I and II
Differential HSTL-18 Class I and II
Programmable pull-up resistor
Open-drain output
Serial, parallel, and dynamic on-chip termination (OCT)
Differential OCT
Programmable pre-emphasis
Programmable equalization
Programmable differential output voltage (V
“I/O Standards Support”
“I/O Banks” on page 6–5
“I/O Structure” on page 6–17
“On-Chip Termination Support and I/O Termination Schemes” on page 6–24
“OCT Calibration” on page 6–32
“Termination Schemes for I/O Standards” on page 6–38
“Design Considerations” on page 6–46
I/O Standard
CCIO
voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V.
(2)
General purpose
General purpose
General purpose
General purpose
General purpose
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
QDRII/RLDRAM II
QDRII/QDRII+/RLDRAM II
General purpose
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
Clock interfaces
PC and embedded system
OD
)
Chapter 6: I/O Features in Stratix IV Devices
Application
February 2011 Altera Corporation
Table 6–1
I/O Standards Support
lists the
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