EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 199
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
f
1
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
Left-Shift Series Termination Control
Stratix IV devices support left-shift series termination control. You can use left-shift
series termination control to get the calibrated OCT R
value of the external reference resistors connected to the RUP and RDN pins. This feature
is useful in applications that require both 25-Ω and 50-Ω calibrated OCT R
V
SSTL-2 Class I and Class II I/O standards, you only need one OCT calibration block
with 50-Ω external reference resistors.
You can enable the left-shift series termination control feature in the ALTIOBUF
megafunction in the Quartus II software. The Quartus II software only allows
left-shift series termination control for 25-Ω calibrated OCT R
reference resistors connected to the RUP and RDN pins. You can only use left-shift series
termination control for the I/O standards that support 25-Ω calibrated OCT R
This feature is automatically enabled if you are using a bidirectional I/O with 25-Ω
calibrated OCT R
For more information about how to enable the left-shift series termination feature in
the ALTIOBUF megafunction, refer to the
Guide.
(Part 2 of 2)
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
CCIO
. For example, if your application requires 25-Ω and 50-Ω calibrated OCT R
I/O Standard
S
and 50-Ω parallel OCT.
Row I/O (Ω)
On-Chip Series Termination Setting
50
—
50
25
50
—
50
—
I/O Buffer (ALTIOBUF) Megafunction User
S
with half of the impedance
Stratix IV Device Handbook Volume 1
S
with 50-Ω external
Column I/O (Ω)
50
25
50
25
50
25
50
25
S
at the same
S
.
S
for
6–27
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