EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 705
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–19. Two PCIe ×8 Links in Six Transceiver Block Devices
Notes to
(1) Stratix IV devices with six transceiver blocks allow a maximum of two PCIe ×8 links occupying four transceiver blocks. You can configure the
(2) You can use a ×4 PCIe configuration in either a master or slave block.
February 2011 Altera Corporation
other two transceiver blocks to implement other functional modes.
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Figure
2–19:
Figure 2–19
EP4SGX230KF40, EP4SGX290KF40, EP4SGX360KF40, EP4SGX530KF40
Transceiver Block
Transceiver Block
Transceiver Block
GXBL1 (Slave)
GXBL0(Master)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBL2
shows two PCIe ×8 links in six transceiver block devices.
Second PCIe
x8 Link
First PCIe
x8 Link
(Note 1), (2)
Transceiver Block
Transceiver Block
Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
GXBR0 (Master)
GXBR1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBR2
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
2–33
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