EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 224
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–4
Figure 7–2. Memory Clock Generation
Notes to
(1) For pin location requirements,refer to the
(2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback required by
(3) To minimize jitter, regional clock networks are required for memory output clock generation.
Stratix IV Device Handbook Volume 1
the ALTMEMPHY megafunction for tracking; therefore, use bidirectional I/O buffers for these pins. For memory interfaces using a differential DQS
input, the input feedback buffer is configured as differential input. For memory interfaces using a single-ended DQS input, the input buffer is
configured as a single-ended input. Using a single-ended input feedback buffer requires that I/O standard’s VREF voltage is provided to that I/O
bank’s VREF pins.
Figure
System Clock (3)
7–2:
1
1
Stratix IV devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Stratix IV devices also provide an independent DQS
logic block for each CQn pin for complementary read-data strobe and clock
operations. In the Stratix IV pin tables, the differential DQS pin pairs are denoted as
DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and
CQn pins. DQSn and CQn pins are marked separately in the pin table. Each CQn pin
connects to a DQS logic block and the shifted CQn signals go to the negative-edge
input registers in the DQ IOE registers.
Use differential DQS signaling for DDR2 SDRAM interfaces running at or above
333 MHz.
DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, and
RLDRAM II common I/O (CIO) interfaces, or unidirectional signals, as in QDR II+,
QDR II SRAM, and RLDRAM II separate I/O (SIO) devices. Connect the
unidirectional read-data signals to Stratix IV DQ pins and the unidirectional
write-data signals to a different DQS/DQ group than the read DQS/DQ group.
Furthermore, the write clocks must be assigned to the DQS/DQSn pins associated to
this write DQS/DQ group. Do not use the CQ/CQn pin-pair for write clocks.
Using a DQS/DQ group for the write-data signals minimizes output skew, allows
access to the write-leveling circuitry (for DDR3 SDRAM interfaces), and allows
vertical migration. These pins also have access to deskewing circuitry (using
programmable delay chains) that can compensate for delay mismatch between signals
on the bus.
The DQS and DQ pin locations are fixed in the pin table. Memory interface circuitry is
available in every Stratix IV I/O bank that does not support transceivers. All the
memory interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II devices.
V CC
External Memory Interface
FPGA LEs
I/O Elements
Handbook.
D
D
Q
Q
Chapter 7: External Memory Interfaces in Stratix IV Devices
1
0
February 2011 Altera Corporation
Memory Interfaces Pin Support
mem_clk (2)
mem_clk_n (2)
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