EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet

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... Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.1 Stratix IV Device Handbook Volume 1 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xv How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xv Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Info-xv Section I. Device Core Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Stratix IV Device Family Overview Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Stratix IV GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Stratix IV E Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Stratix IV GT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Architecture Features ...

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... Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Chapter 4. DSP Blocks in Stratix IV Devices Stratix IV DSP Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Stratix IV Simplified DSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Stratix IV Operational Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Stratix IV Device Handbook Volume 1 Contents © March 2010 Altera Corporation ...

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... LABs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 PLL Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Clock Input Connections to the PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Clock Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Clock Source Control for PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Cascading PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 © March 2010 Altera Corporation v Stratix IV Device Handbook Volume 1 ...

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... Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 Section II. I/O Interfaces Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1 Chapter 6. I/O Features in Stratix IV Devices I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 I/O Standards and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Stratix IV Device Handbook Volume 1 Contents © March 2010 Altera Corporation ...

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... Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Using the R and R Pins in a DQS/DQ Group Used for Memory Interfaces . . . . . . . . . . . . . . . 7- Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface . . . . . . . . . . . 7-27 Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 © March 2010 Altera Corporation vii Stratix IV Device Handbook Volume 1 ...

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... Left and Right PLLs (PLL_Lx and PLL_Rx 8-28 Stratix IV Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 Transmitter Channel-to-Channel Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 Receiver Skew Margin for Non-DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 Stratix IV Device Handbook Volume 1 Contents © March 2010 Altera Corporation ...

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... PS Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 PS Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34 Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47 © March 2010 Altera Corporation ix Stratix IV Device Handbook Volume 1 ...

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... Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Chapter 12. JTAG Boundary-Scan Testing in Stratix IV Devices BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 BST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 BSDL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Stratix IV Device Handbook Volume 1 Contents © March 2010 Altera Corporation ...

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... Chapter 13. Power Management in Stratix IV Devices Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Stratix IV Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Programmable Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Stratix IV External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 © March 2010 Altera Corporation xi Stratix IV Device Handbook Volume 1 ...

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... Stratix IV Device Handbook Volume 1 Contents © March 2010 Altera Corporation ...

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... Chapter 10 Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Revised: Part Number: SIV51010-3.1 Chapter 11 SEU Mitigation in Stratix IV Devices Revised: Part Number: SIV51011-3.1 © March 2010 Altera Corporation Stratix IV Device Handbook Volume March 2010 November 2009 March 2010 November 2009 March 2010 ...

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... Chapter 12 JTAG Boundary-Scan Testing in Stratix IV Devices Revised: Part Number: SIV51012-3.1 Chapter 13 Power Management in Stratix IV Devices Revised: Part Number: SIV51013-3.1 Stratix IV Device Handbook Volume 1 March 2010 March 2010 Chapter Revision Dates © March 2010 Altera Corporation ...

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... Technical training Product literature Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Bold Type with Initial Capital ...

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... A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic. Additional Information © March 2010 Altera Corporation ...

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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © March 2010 Altera Corporation Section I. Device Core IV ® Stratix IV Device Handbook Volume 1 ...

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... I–2 Stratix IV Device Handbook Volume 1 Section I: Device Core © March 2010 Altera Corporation ...

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... Stratix IV GT—up to 531,200 LEs, 27,376 Kbits RAM, 1,288 18 × 18-bit multipliers, ■ and 48 full-duplex CDR-based transceivers 11.3 Gbps The complete Altera high-end solution includes the lowest risk, lowest total cost path to volume using HardCopy portfolio of application solutions customized for end-markets, and the industry ...

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... Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 ■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact Stratix IV Device Handbook Volume 1 Chapter 1: Stratix IV Device Family Overview Feature Summary PCI Express Compiler User Guide. © March 2010 Altera Corporation ...

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... Figure 1–1 shows a high-level Stratix IV GX chip view. Figure 1–1. Stratix IV GX Chip View Note to Figure 1–1: (1) Resource counts vary with device selection, package selection, or both. © March 2010 Altera Corporation (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

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... I/O and Memory Interface PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL General Purpose I/O and Memory Interface © March 2010 Altera Corporation ...

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... Figure 1–3 shows a high-level Stratix IV GT chip view. Figure 1–3. Stratix IV GT Chip View Note to Figure 1–3: (1) Resource counts vary with device selection, package selection, or both. © March 2010 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

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... Transaction layer support for up to two virtual channels (VCs) ■ Stratix IV Device Handbook Volume 1 Chapter 1: Stratix IV Device Family Overview Architecture Features PCI Express Compiler User Guide. © March 2010 Altera Corporation ...

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... On-package and on-chip power supply decoupling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors ■ Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistors © March 2010 Altera Corporation PCI Express Compiler User Guide. Stratix IV Device Handbook Volume 1 1–7 ...

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... (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in Stratix IV GX and Stratix IV GT devices ■ (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in Stratix IV E devices Stratix IV Device Handbook Volume 1 Chapter 1: Stratix IV Device Family Overview Architecture Features © March 2010 Altera Corporation ...

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... Programmable DQ group widths bits (includes parity bits) ■ ■ Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate register capabilities provide a robust external memory interface solution © March 2010 Altera Corporation ) and on-chip parallel (R ) termination with auto-calibration for termination for differential I/Os D ratio of 8:1:1 to reduce loop inductance in the package— ...

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... I/O, power, and the JTAG pins to PCB, refer to the Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines Stratix IV GT Device Family Pin Connection Stratix IV Device Handbook Volume 1 Chapter 1: Stratix IV Device Family Overview Architecture Features and the Guidelines. © March 2010 Altera Corporation ...

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Table 1–1 lists the Stratix IV GX device features. Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option ALMs 29,040 42,240 70,300 LEs 72,600 105,600 175,750 0.6 Gbps- 8.5 Gbps Transceivers — ...

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Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option M9K Blocks (256 × 462 660 950 36 bits) M144K Blocks (2048 × 72 bits) Total Memory (MLAB+M9K+ 7,370 9,564 ...

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... KF40 — — KF40 — — KF40 KF43 NF45 KF40 KF43 NF45 KH40 (3) KF43 NF45 Altera Device Package Information Data Sheet and V (Shared) CCA_L/R CCT CCR 1× 470nF + 1× 47nF per 100nF side 1× 470nF + 1× 47nF per 100nF side ...

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... CCA_L/R CCT CCR 1× 470nF + 1× 47nF per 100nF side 1× 470 nF + 1× 100 nF per side 1× 470 nF + 1× 100nF per side 1× 470 nF + 1× 100 nF per side 1× 470 nF + 1× 100 nF per side Altera Technical Support. ...

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... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (2) Four multiplier adder mode. (3) Total pairs of high-speed LVDS SERDES take the lowest channel count of R (4) This data is preliminary. © March 2010 Altera Corporation EP4SE360 EP4SE530 780 1152 ...

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... Chapter 1: Stratix IV Device Family Overview Architecture Features F1760 (6) (42.5 mm × 42.5 mm) (6) — — — — (3) F43 (3) F43 Altera Device V CCIO 10 nF per bank 10 nF per bank 10 nF per bank EP4S100G4 EP4S100G5 1932 1517 1932 141,440 212,480 353,600 531,200 © March 2010 Altera Corporation ...

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... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (5) This data is preliminary. © March 2010 Altera Corporation EP4S40G5 EP4S100G2 ...

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... Devices under the same arrow sign have vertical migration capability. (2) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Altera Device Package Information Data (3) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm × 42.5-mm Hybrid flip chip packages. ...

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... D: 8 230 F: 16 290 H: 24 360 K: 36 530 N: 48 820 Package Type F: FineLine BGA (FBGA) H: Hybrid FineLine BGA © March 2010 Altera Corporation Ball Array Dimension Corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins 1–19 ...

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... Chapter 1: Stratix IV Device Family Overview Document Revision History Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices Speed Grade with 1 being the fastest Operating Temperature C: Commercial temperature ( Industrial temperature (t = 0°C to 100°C) J Summary of Changes — — — © March 2010 Altera Corporation ...

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... Updated “Table 1–5 shows the total number of transceivers ■ available in the Stratix IV GT Device.” on page 1–15. July 2008 Revised “Introduction”. v1.1 May 2008 Initial Release. v1.0 © March 2010 Altera Corporation Changes Made 1–21 Summary of Changes — — — — — ...

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... Stratix IV Device Handbook Volume 1 Chapter 1: Stratix IV Device Family Overview Document Revision History © March 2010 Altera Corporation ...

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... LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Stratix IV LAB structure and the LAB interconnects. © November 2009 Altera Corporation 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices IV device. You can use these to configure logic functions, ® ...

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... Either Side by Columns & LABs, & from Above by Rows TriMatrix Embedded Memory Blocks in Stratix IV Logic Array Blocks ALMs Direct link interconnect from adjacent block Direct link interconnect to adjacent block Column Interconnects of Variable Speed & Length Figure 2–2. © November 2009 Altera Corporation ...

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... LAB’s local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LAB can drive 30 ALMs through fast-local and direct-link interconnects. © November 2009 Altera Corporation (1) ALM (1) ALM ...

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... Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Local Interconnect LAB Logic Array Blocks Direct-link interconnect from the right LAB, TriMatrix memory block, DSP block, or IOE output ALMs Direct-link interconnect to right © November 2009 Altera Corporation ...

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... Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link. ALM. © November 2009 Altera Corporation There are two unique clock signals per LAB. labclk0 labclk1 ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices carry_in reg_chain_in labclk adder0 D reg0 adder1 D reg1 reg_chain_out carry_out Adaptive Logic Modules To general or local routing To general or Q local routing To general or Q local routing To general or local routing © November 2009 Altera Corporation ...

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... For each set of output drivers, two ALM outputs can drive column, row, or direct-link routing connections. One of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. © November 2009 Altera Corporation syncload aclr[1:0] carry_in clk[2:0] ...

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... Stratix IV ALM single function six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices © November 2009 Altera Corporation Adaptive Logic Modules “LAB Control Signals” ...

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... For the packing of 2 five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). © November 2009 Altera Corporation dataf0 datae0 combout0 datac ...

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... If datae1 and dataf1 are used, the output either drives (Note 1) 6-Input LUT D Q reg0 D Q reg1 labclk shows the template of supported seven-input functions using Figure 2–9 Adaptive Logic Modules To general or local routing To general or local routing To general or local routing occur naturally in designs. © November 2009 Altera Corporation ...

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... ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. Figure 2–10. ALM in Arithmetic Mode datae0 dataf0 datac datab dataa datad datae1 dataf1 © November 2009 Altera Corporation LUT combout0 D reg0 LUT carry_in adder0 4-Input LUT D reg0 4-Input ...

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... MLAB columns, the bottom half can be bypassed. For more information about carry-chain interconnects, refer to on page 2–17. Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices © November 2009 Altera Corporation Adaptive Logic Modules “ALM Interconnects” ...

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... TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. © November 2009 Altera Corporation Figure 2–11 shows the ALM using this feature. shared_arith_in ...

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... Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–17. Figure 2–12 shows the register constructed using two 4-input LUT 5-input LUT Adaptive Logic Modules “ALM sumout LUT regout combout sumout combout © November 2009 Altera Corporation ...

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... LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift-register implementation. These resources speed up connections between ALMs while saving local interconnect resources (refer to advantage of these resources to improve utilization and performance. © November 2009 Altera Corporation reg_chain_in datain aclr aclr datain ...

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... To next ALM within the LAB Adaptive Logic Modules To general or local routing To general or local routing To general or local routing To general or local routing To general or local routing To general or local routing To general or local routing To general or local routing “ALM Interconnects” © November 2009 Altera Corporation ...

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... Stratix IV devices provide a device-wide reset pin (DEV_CLRn) that resets all the registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals. © November 2009 Altera Corporation Figure 2–15 shows the shared arithmetic chain, carry Local interconnect ...

Page 58

... Initial release. v1.0 Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Power Optimization chapter in volume 2 of the Quartus II Changes Made © November 2009 Altera Corporation Document Revision History Summary of Changes — — — — — ...

Page 59

... Total RAM bits (including parity bits) Configurations (depth × width) Parity bits Byte enable Packed mode © March 2010 Altera Corporation 3. TriMatrix Embedded Memory Blocks in Plug-In Manager. You can stitch together multiple blocks of the same MLABs M9K Blocks 600 MHz 600 MHz 640 9216 8K × ...

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... Built-in support in ×64-wide SDP mode or soft IP support using the Quartus II software Total RAM Bits (Including MLABs) (Kb) (Kb) 14,283 17,133 18,144 22,564 20,736 27,376 23,130 33,294 6462 7370 8244 9564 11,430 13,627 14,283 17,133 © March 2010 Altera Corporation ...

Page 61

... Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte enables are active high. 1 You cannot use the byte enable feature when using the error correction coding (ECC) feature on M144K blocks. © March 2010 Altera Corporation Total Dedicated RAM Bits M144K (Dedicated Memory Blocks Only) Blocks ...

Page 62

... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices ABCD 01 11 ABFF FFFF ABXX XXCD ABCD ABFF FFCD ABCD Overview a1 a2 XXXX XX FFCD ABCD ABFF FFCD ABCD ABFF FFCD ABCD © March 2010 Altera Corporation ...

Page 63

... Figure 3–3 shows the address clock enable waveform during the read cycle. Figure 3–3. Address Clock Enable During Read Cycle Waveform inclock rdaddress addressstall latched address (inside memory) q (synch) q (asynch) © March 2010 Altera Corporation 1 address[0] address[0] 0 register 1 address[N] register address[N] ...

Page 64

... Figure 3–5. Output Latch Asynchronous Clear Waveform outclk aclr aclr at latch q Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Overview “Memory Modes” Figure 3–5 © March 2010 Altera Corporation ...

Page 65

... Double error and no fix Illegal Illegal Illegal Illegal 1 You cannot use the byte enable feature when ECC is engaged. 1 Read-during-write “old data mode” is not supported when ECC is engaged. © March 2010 Altera Corporation Internal Memory (RAM and ROM) User eccstatus[2] eccstatus[ ...

Page 66

... This applies to both read and write operations. Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices RAM Array 64 Memory Modes 8 SECDED Comparator Encoder Flag Error Generator Locator 64 3 Status Flags Error Correction Block 64 Data Output © March 2010 Altera Corporation ...

Page 67

... TriMatrix memory blocks in single-port mode. Table 3–4. Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode) Port Width Configurations © March 2010 Altera Corporation Figure 3–7 shows the single-port RAM (Note 1) data[ ] ...

Page 68

... M9K blocks in simple Write Port 2K × × 8 512 × 16 256 × Memory Modes A1 11 EEEE FFFF A1(old data) DDDD EEEE rden q[ ] rdclock 1K × 9 512 × 18 256 × 36 — — — — — — — — — © March 2010 Altera Corporation ...

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... The available choices depend on the configuration of the MLAB. There is no “new data” option for MLABs. © March 2010 Altera Corporation Write Port 2K × × 8 512 × ...

Page 70

... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices dout0 doutn dout0 doutn Memory Modes din4 din5 din6 din4 din5 din6 b2 b3 © March 2010 Altera Corporation ...

Page 71

... Table 3–8 lists the possible M144K block mixed-port width configurations in true dual-port mode. Table 3–8. M144K Block Mixed-Width Configurations (True Dual-Port Mode) (Part Read Port 16K × × × 32 © March 2010 Altera Corporation (Note 1) data_a[ ] data_b[ ] address_a[ ] address_b[] wren_a wren_b ...

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... Memory Modes Write Port 16K × × × din4 din5 din6 din5 dout3 din4 b2 b3 dout2 dout1 © March 2010 Altera Corporation ...

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... Figure 3–14 shows the TriMatrix memory block in shift-register mode. Figure 3–14. Shift-Register Memory Configuration Shift Register m-Bit Shift Register W m-Bit Shift Register W m-Bit Shift Register W m-Bit Shift Register W © March 2010 Altera Corporation 3– Number of Taps W W Stratix IV Device Handbook Volume 1 ...

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... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Guide. Simple Single-Port Mode Dual-Port Mode — — — Clocking Modes SCFIFO and ROM Mode FIFO Mode v — v — v — © March 2010 Altera Corporation ...

Page 75

... MLABs gain input address registers and additional data output registers from ALMs. f For more information about register packing, refer to the Adaptive Logic Modules in Stratix IV Devices © March 2010 Altera Corporation Logic Array Blocks and chapter. Stratix IV Device Handbook Volume 1 3–17 ...

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... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Figure 3–15 shows the difference between the Port A data in Port A data out Design Considerations Port B data in Mixed-port data flow Same-port data flow Port B data out © March 2010 Altera Corporation ...

Page 77

... M9K and M144K blocks. Figure 3–17. M9K and M144K Blocks Same-Port Read-During-Write: New Data Mode clk_a address rdena wrena bytenna data_a q_a (asyn) © March 2010 Altera Corporation FFFF XX FFFF A1(old data) A0(old data) XX ...

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... A0 (old data) B423 A1(old data) old old Internal Memory (RAM and ROM) User A0 A0 AAAA BBBB CCCC DDDD AAAA AABB A0 (old data) Design Considerations A1 11 EEEE FFFF DDDD EEEE A1 A1 EEEE FFFF 10 01 A1(old data) DDDD DDEE © March 2010 Altera Corporation ...

Page 79

... M9K and M144K blocks. Figure 3–21. M9K and M144K Blocks Mixed-Port Read-During Write: Old Data Mode clk_a&b wrena address_a data_a bytenna rdenb address_b q_b_(asyn) © March 2010 Altera Corporation A0 A0 AAAA BBBB CCCC DDDD ...

Page 80

... The Quartus II software automatically places any unused memory blocks in low-power mode to reduce static power. Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices A0 AAAA BBBB CCCC DDDD XXXX (unknown data) Internal Memory (RAM and ROM) Quartus II Handbook. Design Considerations A1 EEEE FFFF 11 A1 © March 2010 Altera Corporation ...

Page 81

... Removed “Referenced Documents” section. ■ November 2008 Updated “Power-Up Conditions and Memory Initialization” on v2.0 page 3–20 May 2008 Initial Release. v1.0 © March 2010 Altera Corporation Changes Made “Simple Dual-Port Mode”, “Same-Port Read-During- “Mixed-Port Read-During-Write Mode” 3–14. 3–23 Summary of Changes sections. — ...

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... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Document Revision History © March 2010 Altera Corporation ...

Page 83

... IV DSP Block Resource Descriptions” on page 4–9 ■ “Stratix IV Operational Mode Descriptions” on page 4–15 “Software Support” on page 4–34 ■ © November 2009 Altera Corporation 4. DSP Blocks in Stratix IV Devices IV device digital signal processing (DSP) ® Stratix IV Device Handbook Volume 1 ...

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... November 2009 Altera Corporation Four Adder Mode 18 × 18 1288 1040 1024 960 384 512 920 1288 832 1040 1024 1024 ...

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... In Stratix IV devices, the fundamental building block is a pair of 18 × 18-bit multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in Equation 4–1 1 All signed numbers, input, and output data are represented in 2’s-complement format only. © November 2009 Altera Corporation Independent Input and Output Multiplication Operators 9 × × × 18 Multipliers ...

Page 86

... Chapter 4: DSP Blocks in Stratix IV Devices P[36.. [17..0] × B [17..0] ± A [17..0] × Figure 4–2 is useful for building more complex structures, Z[37.. [36.. [36.. [43.. [43..0] ± Z [37..0] n n-1 n Stratix IV Simplified DSP Operation [17..0] 1 +/- P[36..0] Equation 4–2 and © November 2009 Altera Corporation ...

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... The 44-bit result is either fed to the next half block or out of the DSP block using the output register stage, as shown in later sections. © November 2009 Altera Corporation provides a sum of four 18 × 18-bit multiplication operations Equation 4–3 provides a four 18 × 18-bit multiplication Figure 4– ...

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... Stratix IV Device Handbook Volume 1 From Previous Half DSP Block 44 To Next Half DSP Block Figure 4–4 is the optional rounding and saturation unit (RSU). This Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Simplified DSP Operation 44 Result[] 44 © November 2009 Altera Corporation ...

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... Figure 4–6 on page 4–9 Figure 4–5. Stratix IV Full DSP Block 144 Input Data 144 Input Data © November 2009 Altera Corporation shows a more detailed top-level view of the DSP block. From Previous Half DSP Block 44 Top Half DSP Block 44 Bottom Half DSP Block To Next Half DSP Block 4– ...

Page 90

... Chainout 1st Stage Stage Adder Add/Sub Add/Acc No No — — — — Yes No — — — — — — Both — Yes Yes Both Add Only Yes Yes Both Both No — — — — Add Only © November 2009 Altera Corporation ...

Page 91

... Block output for accumulator overflow and saturate overflow. (2) Block output for saturation overflow of chainout. (3) The chainin port must only be connected to chainout of the previous DSP blocks and must not be connected to general routings. © November 2009 Altera Corporation shows a list of DSP block dynamic signals. signa ...

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... Stratix IV Device Handbook Volume 1 Figure 4–7. Table 4–9 on page 4–33 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions lists the DSP block dynamic © November 2009 Altera Corporation ...

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... DSP blocks. The dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular FPGA routing resources. © November 2009 Altera Corporation clock[3..0] ena[3..0] aclr[3 ...

Page 94

... Figure 4–15 on page 4–15. Depending on the data width of the Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions Figure 4–6 on page 4–9. In 4–22. 36 × 36 Double v v — — — — 4–23. Table 4–4 shows the © November 2009 Altera Corporation ...

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... The final stage of a 36-bit multiplier ■ A sum of four (18 × 18) An accumulator (44-bits maximum) ■ ■ A chained output summation (44-bits maximum) © November 2009 Altera Corporation Data B (signb Value) Unsigned (logic 0) Signed (logic 1) Unsigned (logic 0) Signed (logic 1) 4–22. shows that the outputs of the multipliers are the only outputs shows that the output from the first-stage adder can either 4– ...

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... Use the first one for performing a four-multiplier adder; use the second for the chainout adder. Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions “Stratix IV Operational Mode Descriptions” on © November 2009 Altera Corporation ...

Page 97

... For operand widths from bits × 12 multiplier is implemented, and for operand widths from bits × 18 multiplier is implemented. This is done by the Quartus II software by zero-padding the LSBs. the independent multiplier operation. signals for the DSP block. © November 2009 Altera Corporation 4–15. Figure 4–8, Figure 4–9, and Figure 4– ...

Page 98

... Figure 4–8: (1) Block output for accumulator overflow and saturate overflow. Stratix IV Device Handbook Volume 1 signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions overflow (1) 36 result_0 result_1[ ] © November 2009 Altera Corporation ...

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... Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–9. 12-Bit Independent Multiplier Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[11..0] datab_0[11..0] dataa_1[11..0] datab_1[11..0] dataa_2[11..0] datab_2[11..0] © November 2009 Altera Corporation signa signb Half-DSP Block 4–17 24 result_0 result_1[ ] ...

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... DSP block to pipeline the multiplier result, increasing the performance of the DSP block. 1 The rounding and saturation logic unit is supported for 18-bit independent multiplier mode only. Stratix IV Device Handbook Volume 1 signa signb Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions 18 result_0 result_1 result_2 result_3[ ] © November 2009 Altera Corporation ...

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... Figure 4–11. 36-Bit Independent Multiplier Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] © November 2009 Altera Corporation signa signb + + Half-DSP Block 4–19 Figure 4–11 result[ ] Stratix IV Device Handbook Volume 1 ...

Page 102

... Figure 4–12. Double Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Stratix IV Device Handbook Volume 1 Figure 4–12 and Figure signa signb + + Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions 4–13 result[ ] © November 2009 Altera Corporation ...

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... November 2009 Altera Corporation clock[3..0] signa ena[3..0] signb aclr[3..0] Two Multiplier "0" Adder Mode "0" + Double Mode Mode Unsigned Multiplier 36 55 108 result[ ] ...

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... Block output for accumulator overflow and saturate overflow. Stratix IV Device Handbook Volume 1 signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate + Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–14 shows overflow (1) result[ ] © November 2009 Altera Corporation ...

Page 105

... This mode automatically assumes all inputs are using signed numbers. © November 2009 Altera Corporation signa signb output_round output_saturate + shows a complex multiplication ...

Page 106

... Equation 4–2 on page 4–4 Stratix IV Device Handbook Volume 1 signa signb Half-DSP Block and Equation 4–3 on page Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Real Part Imaginary Part Figure 4–17, the DSP block can 4–4. © November 2009 Altera Corporation ...

Page 107

... Four-multiplier adder mode supports the rounding and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © November 2009 Altera Corporation signa signb output_round ...

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... Z[54.. [53.. where A[17..0] × B[35.. C[17..0] × D[35..0] 1 Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices [53..0] 1 Stratix IV Operational Mode Descriptions Figure 4–18, the DSP © November 2009 Altera Corporation ...

Page 109

... In multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. The output of the DSP block is looped back to the second-stage adder and added or subtracted with the two outputs of the first-stage adder block according to configured to operate in multiply accumulate mode. © November 2009 Altera Corporation signa signb + P 0 < ...

Page 110

... You must configure the control signal for the accumulator and subtractor is static at compile time. Stratix IV Device Handbook Volume 1 signa signb output_round output_saturate + + + Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions chainout_sat_overflow (1) 44 result[ ] © November 2009 Altera Corporation ...

Page 111

... The barrel shifter uses unsigned input vector and implements a rotation function on a 32-bit word length. Two control signals, rotate and shift_right, together with the signa and signb signals, determine the shifting operation. operations. © November 2009 Altera Corporation Figure 4–20 shows the Table 4–5 shows examples of shift Stratix IV Device Handbook Volume 1 4– ...

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... Signb Shift Rotate A-input 0 0 0xAABBCCDD 1 0 0xAABBCCDD 0 0 0xAABBCCDD 1 0 0xAABBCCDD 0 1 0xAABBCCDD Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions 32 result[ ] B-input Result 0x0000100 0xBBCCDD00 0x0000100 0x000000AA 0x0000100 0xBBCCDD00 0x0000100 0xFFFFFFAA 0x0000100 0xBBCCDDAA © November 2009 Altera Corporation ...

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... Table 4–7. Comparison of Round-to-Nearest-Integer and Round-to-Nearest-Even Round-To-Nearest-Integer © November 2009 Altera Corporation shows how round-to-nearest-even works. Table 4–7 shows the main difference between the two Odd/Even Fractional (Integer) x > 0.5 (11) x < 0.5 (01) Even (0010 ...

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... Stratix IV Device Handbook Volume 1 (n– For example, for 32 bits: (n–1) Symmetric SAT Result 7FFFFFFFFh 800000001h 4–21 User defined RND Positions (bit 21- Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions – 1. Symmetrical saturation limits Asymmetric SAT Result 7FFFFFFFFh 800000000h © November 2009 Altera Corporation ...

Page 115

... Q-format multiply. If both rounding and saturation is enabled, saturation is done on the rounded result. chainout_saturate chainout_saturate = 1 for saturation support chainout_saturate = 0 for no saturation support © November 2009 Altera Corporation S (A × B)], when used for an accumulation type of operation × B)], when used for an accumulation type of operation. ...

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... DSP block-wide asynchronous clear signals (active low). aclr2 aclr3 Total Count per Full Block Software Support Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: ■ lpm_mult ■ ...

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... Updated Table 4–2. ■ November 2008 Updated Figure 4–16. ■ v2.0 Updated Figure 4–18. ■ May 2008 Initial Release. v1.0 © November 2009 Altera Corporation “Synthesis” section in volume 1 of the Quartus II Changes Made 4–1. section. 4–35 Summary of Changes — — — ...

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... Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Document Revision History © November 2009 Altera Corporation ...

Page 119

... There are 80 GCLKs/RCLKs per entire device in the EP4S40G2, EP4S100G2, EP4SE230, EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 devices. There are 104 GCLKs/RCLKS per entire device in the EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530, EP4SE820, EP4SGX290, EP4SGX360, and EP4SGX530 devices. © March 2010 Altera Corporation 5. Clock Networks and PLLs in IV devices. It includes details about the ® ...

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... Figure 5–1. GCLK Networks L1 L2 CLK[0.. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–1 through Guidelines. CLK[12..15 GCLK[12..15] GCLK[0..3] GCLK[8..11] GCLK[4.. CLK[4..7] Clock Networks in Stratix IV Devices Figure 5–4 on page 5–4. Stratix CLK[8..11 © March 2010 Altera Corporation ...

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... A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and another four core signals can drive into RCLK[54..63] at any one time. © March 2010 Altera Corporation Figure 5–4 on page 5–4 show the CLK pins and PLLs that can CLK[12 ...

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... Q4 Q3 RCLK[6..11] RCLK[32..37] RCLK[12..21] RCLK[22..31 CLK[4..7] (Note 1), (2), (3) CLK[12..15 RCLK[82..87] RCLK[54..63] RCLK[44..53] RCLK[76..81] RCLK[0..5] RCLK[38..43 RCLK[6..11] RCLK[32..37] RCLK[64..69] RCLK[70..75] RCLK[12..21] RCLK[22..31 CLK[4..7] Clock Networks in Stratix IV Devices (Note 1) R2 CLK[8..11 CLK[8..11 Table 5–6 on Table 5–7 on page 5–19. © March 2010 Altera Corporation ...

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... Legal clock sources for PCLK networks are clock outputs from the DPA block, PLD-transceiver interface clocks, horizontal I/O pins, and internal logic. Figure 5–5. PCLK Networks (EP4SGX70 and EP4SGX110 Devices) L2 CLK[0..3] © March 2010 Altera Corporation Figure 5–5 to Figure 5–8 on page 5–7 CLK[12..15] T1 PCLK[0 ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices CLK[12..15 PCLK[0..10] PCLK[77..87] PCLK[11..21] PCLK[66..76 PCLK[22..32] PCLK[55..65] PCLK[33..43] PCLK[44..54 CLK[4..7] CLK[12..15 PCLK[98..111] PCLK[0..13] PCLK[14..27] PCLK[84..97 PCLK[28..41] PCLK[70..83] PCLK[42..55] PCLK[56..69 CLK[4..7] Table 5–7 on page Clock Networks in Stratix IV Devices R2 CLK[8..11] R3 Table 5– CLK[8..11 5–19. © March 2010 Altera Corporation ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices Figure 5–8. PCLK Networks (EP4SE820 Device CLK[0.. © March 2010 Altera Corporation CLK[12..15 PCLK[0..15] PCLK[116..131] PCLK[16..32] PCLK[99..115 PCLK[33..49] PCLK[82..98] PCLK[50..65] PCLK[66..81 CLK[4..7] 5– CLK[8..11 Stratix IV Device Handbook Volume 1 ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–9 16 GCLK 3 (4) SCLK 16 (2) PCLK 22 (3) RCLK Clock Networks in Stratix IV Devices shows that the SCLKs can be driven (Note 1) 9 Column I/O clock 26 3 Core reference clock 6 Row clock (7) © March 2010 Altera Corporation (5) (6) ...

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... Corner PLL outputs only span one quadrant, they cannot generate a dual-regional clock network. Figure 5–10. Stratix IV Dual-Regional Clock Region © March 2010 Altera Corporation Figure 5–10 shows the dual-regional clock region. Clock pins or PLL outputs can drive half of the device to ...

Page 128

... March 2010 Altera Corporation ...

Page 129

... RCLK [32, 36, 38, — — 42] RCLK [47, 51, 57, — — 61] RCLK [46, 50, 56, — — 60] RCLK [45, 49, 53, — — 55, 59, 63] RCLK [44, 48, 52, — — 54, 58, 62] © March 2010 Altera Corporation CLK (p/n Pins — — — — — — — — — — — — ...

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... March 2010 Altera Corporation T2 — — — — — — — — — — — — T2 — — — — ...

Page 131

... Every GCLK and RCLK network has its own clock control block. The control block provides the following features: ■ Clock source selection (dynamic selection for GCLKs) ■ Global clock multiplexing ■ Clock power down (static or dynamic clock enable or disable) © March 2010 Altera Corporation PLL Number — ...

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... GCLK and RCLK select blocks, respectively. CLKp Pins 2 PLL Counter 2 CLKn Outputs 2 CLKSELECT[1..0] (1) This multiplexer supports user-controllable dynamic switching Enable/ Disable GCLK Clock Networks in Stratix IV Devices Pin Internal Logic Static Clock Select (2) Internal Logic © March 2010 Altera Corporation ...

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... PLL outputs feed the inclk[2..3] ports. You can choose from among these inputs using the CLKSELECT[1..0] signal. f For more information, refer to the User Guide. © March 2010 Altera Corporation CLKp CLKn (2) Pin Pin PLL Counter 2 ...

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... Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLL Counter Outputs Static Clock Select Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL_<#>_CLKOUT pin (1) (1) ( Clock Networks in Stratix IV Devices (1) GCLK/ RCLK/ PLL_<#>_CLKOUT (1) © March 2010 Altera Corporation ...

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... The Quartus II software automatically sets the multiplexer select signals depending on the clock sources selected in the design. © March 2010 Altera Corporation Figure 5–15 shows a waveform example for Figure 5–16; the corresponding clock ...

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... Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 4 clk[n+3..n] (2) Adjacent PLL output 4 PLL_<L1/L4/R1/R4>_CLK (1) GCLK/RCLK (2) 4 CLK[0..3] or CLK[8..11] (3) 4 Stratix IV Transceiver Clocking chapter. Clock Networks in Stratix IV Devices (1) inclk0 To the clock switchover block (1) inclk1 inclk0 inclk1 © March 2010 Altera Corporation ...

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... EP4SE530 H1517 v F1760 H1152 — v EP4SE820 H1517 v F1760 F780 — EP4SGX70 F1152 — F780 — EP4SGX110 F1152 — F780 — EP4SGX180 F1152 — F1517 — F780 — EP4SGX230 F1152 — F1517 — © March 2010 Altera Corporation — — — — ...

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... Single-ended only Yes (1) Through GCLK and RCLK and dedicated path between adjacent PLLs (2) All except external feedback mode when using differential I/Os Yes Yes Down to 96.125 ps (3) Yes Yes © March 2010 Altera Corporation R4 — — — — — — — — ...

Page 139

... The PFD produces down signal that determines whether the VCO must operate at a higher or lower frequency. The output of the PFD feeds the charge pump and loop filter, which produces a control voltage for setting the © March 2010 Altera Corporation Stratix IV Top/Bottom PLLs Yes ° ...

Page 140

... Casade output to adjacent PLL /2, /4 ÷C0 GCLKs 8 ÷C1 ÷2 RCLKs 8 (2) External clock ÷C2 outputs DIFFIOCLK from ÷C3 Left/Right PLLs LOAD_EN from Left/Right PLLs (1) ÷Cn FBOUT (3) External ÷m memory interface DLL FBIN DIFFIOCLK network GCLK/RCLK network © March 2010 Altera Corporation ...

Page 141

... I/Os or one differential I/O pair. When using both pins as single-ended I/Os, one of them can be the clock output while the other pin is the external feedback input (FB) pin. Therefore, for single-ended I/O standards, the left and right PLLs only support external feedback mode. © March 2010 Altera Corporation clkena4 (3) clkena2 (3) clkena3 (3) clkena5 (3) PLL_< ...

Page 142

... You can also use the external clock output pins as user I/O pins if you do not need external PLL clocking. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices LEFT/RIGHT C3 PLLs m(fbout) clkena0 (3) clkena1 (3) PLL_<L2, L3, R2, R3>_FB_CLKOUT0p/CLKOUT0n (1), (2) I/O Features in Stratix IV Devices PLLs in Stratix IV Devices Internal Logic chapter. © March 2010 Altera Corporation ...

Page 143

... Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL. © March 2010 Altera Corporation 5– ...

Page 144

... IOE input register. Figure 5–22 shows an example waveform of the clock and data in this mode. Altera recommends source synchronous mode for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard ...

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... Data pin-to-SERDES capture register ■ ■ Clock input pin-to-SERDES capture register. In addition, the output counter must provide the 180° phase shift © March 2010 Altera Corporation Data pin PLL reference clock at input pin Data at register Clock at register 5– ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Data pin PLL reference clock at input pin Data at register Clock at register Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port (1) PLLs in Stratix IV Devices Figure 5–24 shows an example © March 2010 Altera Corporation ...

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... The bi-directional I/O pin that you instantiate in your design must always be assigned a single-ended I/O standard. 1 When using ZDB mode, to avoid signal reflection, do not place board traces on the bi-directional I/O pin. © March 2010 Altera Corporation Figure 5–25 shows an example waveform of the PLL clocks’ phase Phase Aligned PLL Reference Clock at the ...

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... PFD CP/LF VCO ÷C1 fbout ÷m Phase Aligned PLL Reference Clock at the Input Pin Dedicated PLL Clock Outputs Figure 5–28. Aligning these clocks allows you to PLLs in Stratix IV Devices PLL_<#>_CLKOUT# PLL_<#>_CLKOUT# bidirectional I/O pin fbin © March 2010 Altera Corporation ...

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... PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz (the least common multiple of 33 and 66 MHz within the VCO range). Then the post-scale counters scale down the VCO frequency for each output port. © March 2010 Altera Corporation Phase Aligned PLL Reference Clock at the ...

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... Post-scale counter cascading is set in the configuration file. You cannot set this using PLL reconfiguration. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices VCO Output C0 C1 VCO Output C2 VCO Output C3 VCO Output C4 VCO Output Cn VCO Output (1) PLLs in Stratix IV Devices Figure 5–30. from preceding post-scale counter © March 2010 Altera Corporation ...

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... Equation 5–1. Fine-Resolution Phase Shift where f is the input reference clock frequency. REF For example 156.25 ps. This phase shift is defined by the PLL operating frequency, which is governed by the reference clock frequency and the counter settings. © March 2010 Altera Corporation 1 1 Φ ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices shows the coarse-resolution phase shifts are implemented by delaying C − 1 Φ coarse Φ . CLK2 is based on the 0phase from the VCO but has the FINE t VCO PLLs in Stratix IV Devices (C − 1)N Mf REF Φ (two COARSE © March 2010 Altera Corporation ...

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... Figure 5–32. Open- and Closed-Loop Response Bode Plots Open-Loop Reponse Bode Plot 0 dB Gain Closed-Loop Reponse Bode Plot Gain © March 2010 Altera Corporation Figure 5–32 shows, these points correspond to approximately the same Frequency Frequency 5–35 Increasing the PLL's bandwidth in effect pushes the open loop response out ...

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... Quartus II software. The components are the loop filter resistor, R, the high frequency capacitor and the charge pump current Figure 5–33. Loop Filter Programmable Components Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PFD I DN PLLs in Stratix IV Devices . © March 2010 Altera Corporation ...

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... PLL to implement a custom switchover circuit in the logic array. You can select a clock source as the backup clock by connecting it to the inclk1 port of the PLL in your design. © March 2010 Altera Corporation 5–37 Figure 5–34 Stratix IV Device Handbook Volume 1 ...

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... Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover. In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs ...

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... VCO operates within the recommended operating frequency range of 600 to 1,600 MHz. The ALTPLL MegaWizard Plug-in Manager notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement. © March 2010 Altera Corporation inclk0 inclk1 (1) muxout clkbad0 ...

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... Figure 5–37 Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 shows a block diagram of the manual switchover circuit. PLLs in Stratix IV Devices (Note 1) © March 2010 Altera Corporation ...

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... PLL is important in your design. Assert areset for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the PLL. © March 2010 Altera Corporation Clock Switch Control Logic n Counter ...

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... Pre-scale counter (n) ■ ■ Feedback counter (m) Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices shows how the VCO frequency gradually decreases when the current Switchover Occurs PLLs in Stratix IV Devices VCO Tracks Secondary Clock © March 2010 Altera Corporation ...

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... This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The K counter is physically located after the VCO. 1 The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, all counters are not updated simultaneously. © March 2010 Altera Corporation (Note 1) LF/K/CP (3) PFD /C2 /C1 counters. 5– ...

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... Logic array or I/O pin Logic array or I/O pin PLL reconfiguration circuit PLL reconfiguration circuit PLLs in Stratix IV Devices Destination PLL reconfiguration circuit PLL reconfiguration circuit PLL reconfiguration circuit PLL reconfiguration circuit Logic array or I/O pins Logic array or I/O pins © March 2010 Altera Corporation ...

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... The PLL implements this duty cycle by transitioning the output clock from high to low on the rising edge of the VCO output clock. However and 6 setting for the high- and low-count values, respectively, produces an output clock with a 40% - 60% duty cycle. © March 2010 Altera Corporation 5–45 (MSB) Dn Dn_old ...

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... Charge Pump Current VCO Post-Scale divider (K) Loop Filter Capacitor Loop Filter Resistor Unused CP/LF Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Number of Bits Counter PLLs in Stratix IV Devices Table 5–11 lists the Total Other ( © March 2010 Altera Corporation ...

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... Left and right PLLs have the same scan-chain order. The post-scale counters end at C6. Figure 5–42 shows the scan-chain bit-order sequence for post-scale counters in all Stratix IV PLLs. Figure 5–42. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix IV PLLs DATAOUT 0 1 © March 2010 Altera Corporation Number of Bits Counter — LSB DATAOUT C8 C9 ...

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... Table 5–14. Loop-Filter Capacitor Bit Settings LFC[ Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices CP[1] CP[ LFR[3] LFR[2] LFR[ LFC[ PLLs in Stratix IV Devices Decimal Value for Setting LFR[0] Decimal Value for Setting Decimal Value for Setting © March 2010 Altera Corporation ...

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... C counters. This signal is registered in the PLL on the rising edge of SCANCLK. Selects dynamic phase shift direction UP DOWN. Signal is registered in the PLL on the PHASEUPDOWN rising edge of SCANCLK. Logic high enables dynamic phase shifting. PHASESTEP © March 2010 Altera Corporation PLL Scan Chain Bits [0..8] Settings ...

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... PLLs in Stratix IV Devices Source Destination PLL reconfiguration circuit Logic array or I/O pins [0] Selects 0 All Output Counters 1 M Counter 0 C0 Counter 1 C1 Counter 0 C2 Counter 1 C3 Counter 0 C4 Counter 1 C5 Counter 0 C6 Counter 1 C7 Counter 0 C8 Counter 1 C9 Counter © March 2010 Altera Corporation ...

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... PHASESTEP pulses must be at least one SCANCLK cycle apart. f For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer to the Phase-Locked Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide. © March 2010 Altera Corporation Figure b c PHASEDONE goes low synchronous with SCANCLK 5–51 Figure 5– ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices chapter. Changes Made 5–3. Figure 5–2, Figure 5–3, Figure 5–4, and Table 5–5 and Table 5–6. Table 5–4. 5–43. “Dynamic Phase-Shifting” section. Chapter Revision History DC and Switching Summary of Changes — — — — — © March 2010 Altera Corporation ...

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... Updated Figure 5–15. ■ November 2008 v2.0 Updated Figure 5–20 ■ Added Figure 5–21 ■ Made minor editorial changes. ■ May 2008 Initial Release. v1.0 © March 2010 Altera Corporation Changes Made . . 5–53 Summary of Changes — — Stratix IV Device Handbook Volume 1 ...

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... Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Chapter Revision History © March 2010 Altera Corporation ...

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... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © March 2010 Altera Corporation Section II. I/O Interfaces IV device I/O features, external memory ® ...

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... II–2 Stratix IV Device Handbook Volume 1 Section II: I/O Interfaces Revision History © March 2010 Altera Corporation ...

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... Programmable output current strength ■ ■ Programmable slew rate ■ Programmable delay ■ Programmable bus-hold circuit Programmable pull-up resistor ■ © March 2010 Altera Corporation 6. I/O Features in Stratix IV Devices ® IV devices provide I/O capabilities that allow you Stratix IV Device Handbook Volume 1 ...

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... PC and embedded system DDR SDRAM DDR2 SDRAM DDR3 SDRAM QDRII/RLDRAM II QDRII/QDRII+/RLDRAM II General purpose DDR SDRAM DDR2 SDRAM DDR3 SDRAM Clock interfaces Clock interfaces Chapter 6: I/O Features in Stratix IV Devices I/O Standards Support ) Table 6–1 lists the Application © March 2010 Altera Corporation ...

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... JESD8-15 (2) SSTL-15 Class I — (2) SSTL-15 Class II — (2) HSTL-18 Class I JESD8-6 (2) HSTL-18 Class II JESD8-6 (2) © March 2010 Altera Corporation I/O Standard Clock interfaces High-speed communications Flat panel display Flat panel display Video graphics and clock distribution CCIO 6–19. chapter. , and board V . REF TT ...

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... March 2010 Altera Corporation ...

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... PLL_R[1,4]_clk pins, which support differential input operations only. f For the number of channels available for the LVDS I/O standard, refer to the High-Speed Differential I/O Interface and DPA in Stratix IV Devices information about transceiver-bank-related features, refer to the Architecture chapter. © March 2010 Altera Corporation (Note 1) (Part (V) C CIO Output Operation ...

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... LVPECL, which is supported on clk input pins only. Bank 4C Bank 3C when configured as differential clock inputs. They are powered by V CCCLKIN . CCIO Chapter 6: I/O Features in Stratix IV Devices I/O Banks (8) Bank 7B Bank 7A Bank 4B Bank 4A when configured as CCIO © March 2010 Altera Corporation ...

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... Column and row I/O banks support LVPECL standards for input clock operation. (8) Figure 6– top view of the silicon die that corresponds to a reverse view for flip chip packages graphical representation only. © March 2010 Altera Corporation (Note 1), (2), (3), (4), (5), (6), (7), (8) ...

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... This is shown in Figure 6–3. Figure 6–3. Bank Migration Path with Increasing Device Size Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices show the number of I/O pins available in each I/O bank I/O Banks Figure 6–4 48 © March 2010 Altera Corporation ...

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... I/Os Bank Name 48 Bank 1A 42 Bank 1C 42 Bank 2C 48 Bank 2A © March 2010 Altera Corporation Figure 6–16 show the number of I/O pins and packaging through Figure 6–16, the pin count includes all general purpose I/Os, Bank Name Bank 1A Bank 6A EP4SE230 Bank 1C ...

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... Bank 6B 24 Bank 6C 42 EP4SE530 EP4SE820 Bank 5C 42 Bank 5B 24 Bank 5A 50 Bank Name Number of I/Os Bank 6A 50 Bank 6B 36 Bank 6C 50 EP4SE530 EP4SE820 Bank 5C 50 Bank 5B 36 Bank 5A 50 Bank Name Number of I/Os © March 2010 Altera Corporation I/O Banks ...

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... FineLine BGA Package Number of I/ Figure 6–9. Number of I/Os in Each Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package Number of I/Os Number of Transceiver Channels © March 2010 Altera Corporation Number of Transceiver Channels Bank Name Bank 1A EP4SGX70 Bank 1C EP4SGX110 EP4SGX180 EP4SGX230 Bank 2C ...

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... EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 Chapter 6: I/O Features in Stratix IV Devices I/O Banks Bank 6A 32 Bank 6C 26 Bank 4* GXBR1 Bank 4* GXBR0 Bank Name Number of I/Os 48 Bank 6A Bank 6C 42 Bank 4 (2) GXBR1 Bank 4 (2) GXBR0 Bank Name Number of I/Os © March 2010 Altera Corporation ...

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... Bank 2A Bank 4 (1) GXBL2 Bank 4 (1) GXBL1 Bank 4 (1) GXBL0 Note to Figure 6–12: (1) There are two additional PMA-only transceiver channels in each transceiver bank. © March 2010 Altera Corporation (Note 1) EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 Bank 6A 48 Bank 6C 42 Bank 5C 42 Bank 5A ...

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... There are two additional PMA-only transceiver channels in each transceiver bank. Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices Bank 6A Bank 6C Bank 5C Bank 5B Bank 5A EP4SGX530 Bank EP4SGX290 4 (1) GXBR3 EP4SGX360 Bank 4 (1) GXBR2 Bank 4 (1) GXBR1 Bank 4 (1) GXBR0 Bank Name Number of I/Os © March 2010 Altera Corporation I/O Banks ...

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... Bank 2A Bank 4 (1) GXBL2 Bank 4 (1) GXBL1 Bank 4 (1) GXBL0 Note to Figure 6–14: (1) There are two additional PMA-only transceiver channels in each transceiver bank. © March 2010 Altera Corporation Bank 6A 50 Bank 6C 42 Bank 5C 42 EP4SGX290 EP4SGX360 Bank 5A 50 EP4SGX530 Bank 4 (1) ...

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... Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices Bank 6A 38 Bank 6C 22 Bank 5C 19 EP4S100G3 12 Bank 5B EP4S100G4 EP4S100G5 Bank 5A 42 Bank 4 (1) GXBR2 Bank 4 (1) GXBR1 Bank 4 (1) GXBR0 Bank Name Number of I/Os © March 2010 Altera Corporation I/O Banks ...

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... Programmable slew rate ■ Programmable output delay Programmable bus-hold ■ Programmable pull-up resistor ■ ■ Open-drain output ■ On-chip series termination with calibration © March 2010 Altera Corporation Bank 6A 44 Bank 6C 23 Bank 5C 23 EP4S40G2 EP4S40G5 EP4S100G2 Bank 5A 46 EP4S100G5 ...

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... Chapter 6: I/O Features in Stratix IV Devices I/O Structure DQS Logic Block D6_OCT D5_OCT Dynamic OCT Control (2) V CCIO Delay V CCIO PCI Clamp Programmable Pull-Up Resistor From OCT Calibration Block Output Buffer On-Chip Termination Input Buffer Bus-Hold Circuit chapter. © March 2010 Altera Corporation ...

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... To ensure device reliability and proper operation, when interfacing with a 3.3-V I/O system using Stratix IV devices, ensure that you do not violate the absolute maximum ratings of the devices. Altera recommends performing IBIS simulation to determine that the overshoot and undershoot voltages are within the guidelines. ...

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... OCT R without calibration for all non-voltage reference and S Ω OCT R without calibration for HSTL and SSTL S and V at 3.0 V. CCIO CCPD © March 2010 Altera Corporation I/O Structure — 16 — — ...

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... You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. 1 Altera recommends performing IBIS or SPICE simulations to determine the best slew rate setting for your specific application. © March 2010 Altera Corporation 6– ...

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... Bus-hold circuitry uses a resistor with a nominal resistance ( Ω to weakly pull the signal level to the last-driven state. Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices chapter. 6–18. The delay chains can independently control the chapter. © March 2010 Altera Corporation I/O Structure Figure 6– CCIO ) of approximately BH ...

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... VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems.) f For more information about pin connection guidelines, refer to the Family Pin Connection © March 2010 Altera Corporation chapter. level. CCIO chapter. OD swing improves voltage margins at the receiver end ...

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... Stratix (2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3 3.3 V. You have the option to use an internal clamping diode for column I/O pins. (3) Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one V is not supported when ...

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... For the SSTL Class II standard, you must select the 25- Ω on-chip series termination setting (to match the 50- Ω transmission line and the near-end external 50- Ω pull- © March 2010 Altera Corporation through an external 25- Ω ±1% or 50- Ω ±1% CCIO through an external 50- Ω ...

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... On-Chip Termination Support and I/O Termination Schemes Figure 6–19 is the intrinsic impedance of the transistors. Calibration Stratix IV Driver Series Termination V CCIO Ω GND On-Chip Series Termination Setting Row I/O (Ω Chapter 6: I/O Features in Stratix IV Devices Receiving Device Column I/O (Ω © March 2010 Altera Corporation ...