EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 91
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
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- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
February 2011 Altera Corporation
A feature of the input register bank is to support a tap delay line. Therefore, the top
leg of the multiplier input (A) can be driven from general routing or from the cascade
chain, as shown in
signals.
Figure 4–7. Input Register of a Half DSP Block
At compile time, you must select whether the A-input comes from general routing or
from the cascade chain. In cascade mode, the dedicated shift outputs from one
multiplier block and directly feeds the input registers of the adjacent multiplier below
it (within the same half DSP block) or the first multiplier in the next half DSP block, to
form an 8-tap shift register chain per DSP Block. The DSP block can increase the
length of the shift register chain by cascading to the lower DSP blocks. The dedicated
shift register chain spans a single column, but you can implement longer shift register
chains requiring multiple columns using the regular FPGA routing resources.
datab_2[17..0]
dataa_3[17..0]
datab_3[17..0]
dataa_1[17..0]
datab_1[17..0]
dataa_2[17..0]
dataa_0[17..0]
datab_0[17..0]
loopback
scanina[17..0]
Figure
4–7.
clock[3..0]
Table 4–9 on page 4–34
ena[3..0]
aclr[3..0]
Register
Delay
scanouta
signa
signb
+/-
+/-
lists the DSP block dynamic
Stratix IV Device Handbook Volume 1
4–11
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