EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 54
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–18
Stratix IV Device Handbook Volume 1
ALM Interconnects
Clear and Preset Logic Control
There are three dedicated paths between the ALMs—register cascade, carry chain,
and shared arithmetic chain. Stratix IV devices include an enhanced interconnect
structure in LABs for routing shared arithmetic chains and carry chains for efficient
arithmetic functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect. The
Quartus II Compiler automatically takes advantage of these resources to improve
utilization and performance.
chain, and register chain interconnects.
Figure 2–15. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
LAB-wide signals control the logic for the register ’s clear signal. The ALM directly
supports an asynchronous clear function. You can achieve the register preset through
the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to
two clears.
Stratix IV devices provide a device-wide reset pin (DEV_CLRn) that resets all the
registers in the device. An option set before compilation in the Quartus II software
controls this pin. This device-wide reset overrides all other control signals.
routing to adjacent ALM
Carry chain & shared
arithmetic chain
interconnect
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Figure 2–15
Local
Local interconnect
routing among ALMs
in the LAB
shows the shared arithmetic chain, carry
ALM 10
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
Register chain
routing to adjacent
ALM's register input
February 2011 Altera Corporation
Adaptive Logic Modules
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