EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet
EP4SGX530HH35C2N
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EP4SGX530HH35C2N Summary of contents
Page 1
... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. April 2011 Altera Corporation Section I. Device Datasheet and Addendum for Stratix IV Devices Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum ...
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... I–2 Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Section I: Device Datasheet and Addendum for Stratix IV Devices April 2011 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
Page 4
... V -0.5 1.35 V -0.5 1.35 V -0.5 1.8 V -0.5 1.8 V (Note 1) (Part Minimum Maximum Unit -0.5 3.75 V -0.5 3.75 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.8 V April 2011 Altera Corporation ...
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... CCH_GXBRn Notes to Table 1–3: (1) For the absolute maximum ratings for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative. ( Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Table 1– ...
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... RAMP Notes to Table 1–5: (1) If you do not use the volatile security key, you may connect the V (2) V must be 2.5 V when V is 2.5, 1.8, 1. CCPD CCIO April 2011 Altera Corporation Condition Minimum — 0.87 — 0.92 — 1.45 — 2.375 — ...
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... Transmitter power (right side) CCT_R V (3) Transceiver clock power (left side) CCL_GXBLn V (3) Transceiver clock power (right side) CCL_GXBRn V (3) Transmitter output buffer power (left side) CCH_GXBLn April 2011 Altera Corporation Description Minimum 2.85/2.375 0.87 0.87 1.045 1.045 1.045 1.045 1.05 1.05 1.33/1.425 Description Minimum 3 ...
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... Table 1–7: (1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative. (2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating conditions could lead to unpredictable link behavior. ...
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... OCT calibration accuracy is valid at the time of calibration only. Ω (2) 25 not supported for 1.5 V and 1 Row I/O. S Ω (3) 20 not supported for 1.5 V and 1 Row I/O. S April 2011 Altera Corporation V 1.2 V 1.5 V 1.8 V Min Max Min Max Min — 120 — ...
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... OCT resistance value at power-up. SCAL (3) ΔT is the variation of temperature with respect to the temperature at power-up. (4) ΔV is the variation of voltage with respect to the V (5) dR/dT is the percentage change of R (6) dR/dV is the percentage change of R April 2011 Altera Corporation Conditions V = 3.0 and 2.5 V CCIO ...
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... Notes to Table 1–14: (1) The I/O ramp rate more. For ramp rates faster than 10 ns, |I capacitance and dv/dt is the slew rate. (2) These specifications are preliminary. April 2011 Altera Corporation Description OCT variation with voltage without re-calibration OCT variation with temperature without re-calibration range of ± ...
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... Table 1–17. Single-Ended I/O Standards (Part (V) CCIO I/O Standard Min Typ Max LVTTL 2.85 3 3.15 LVCMOS 2.85 3 3.15 April 2011 Altera Corporation Table 1–15 lists the hysteresis specifications across the supported Description Condition ( 3.3 CCIO V = 2.5 Hysteresis for Schmitt CCIO trigger input V = 1.8 CCIO ...
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... Class II 0.15 0.15 SSTL- REF -0.3 Class I 0.125 0.125 SSTL- REF -0.3 Class II 0.125 0.125 SSTL- REF — Class I 0.1 April 2011 Altera Corporation V ( Min Max Min Max -0.3 0.7 1.7 3.6 0. CCIO -0 0.3 CCIO CCIO 0. CCIO -0.3 ...
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... CCIO I/O Standard Min Typ Max HSTL-18 1.71 1.8 1.89 Class I HSTL-15 1.425 1.5 1.575 Class I, II HSTL-12 1.14 1.2 1.26 Class I, II April 2011 Altera Corporation V (V) V (V) V (V) IH(DC) IL(AC) IH(AC) Min Max Max Min + REF REF REF — ...
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... Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F MAX 0.45 V; the maximum input voltage is 1.95 V. Power Consumption Altera offers two ways to estimate power consumption for a design the Excel-based Early Power Estimator and the Quartus 1 You typically use the interactive Excel-based Early Power Estimator before designing the FPGA to get a magnitude estimate of the device power ...
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... REFCLK pin Absolute V for a MIN — REFCLK pin Rise/fall time (21) — Duty cycle — April 2011 Altera Corporation and the PowerPlay Power Analysis chapter in the Quartus II –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ ...
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... Delta time between — (19) reconfig_clks Transceiver block minimum power-down — (gxb_powerdown) pulse width April 2011 Altera Corporation –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 200 — ...
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... V = 0.82 V ICM setting V ICM V = 1.1 V ICM setting (6) Receiver DC Coupling — Support April 2011 Altera Corporation –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS 600 — ...
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... Receiver CDR 1.25 Gbps 3 dB Bandwidth in lock-to-data (LTD) Serial RapidIO mode 2.5 Gbps Serial RapidIO 3.125 Gbps GIGE SONET OC12 SONET OC48 April 2011 Altera Corporation –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 85 ± ...
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... V 0.65 V setting OCM 85− Ω setting 100− Ω setting Differential on-chip termination resistors 120− Ω setting 150-Ω setting April 2011 Altera Corporation –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ Max ...
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... Example: XAUI, skew PCIe ×4, Basic ×4 Inter-transceiver block ×8 PMA and PCS transmitter bonded mode channel-to-channel Example: PCIe ×8, skew Basic ×8 April 2011 Altera Corporation Commercial/Industrial –2 Commercial Speed Grade –2× Commercial Speed Grade Min Typ Max Min =4), ...
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... Gbps XAUI Serial RapidIO -3 dB Bandwidth 1.25 Gbps Serial RapidIO 2.5 Gbps Serial RapidIO 3.125 Gbps GIGE SONET OC12 SONET OC48 April 2011 Altera Corporation –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ — ...
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... PCIe Gen Bandwidth (OIF) CEI PHY at 6.375 Gbps Transceiver-FPGA Fabric Interface Interface speed — (non-PMA Direct) Interface speed — (PMA Direct) April 2011 Altera Corporation –3 Commercial/Industrial –2 Commercial and Speed Grade –2× Commercial Speed Grade Min Typ Max Min ...
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... The rise and fall time transition is specified from 20% to 80%. (22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the April 2011 Altera Corporation Commercial/Industrial –2 Commercial Speed Grade – ...
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... MAX — REFCLK pin Operational V for a MAX — REFCLK pin Absolute V for a MIN — REFCLK pin Rise/fall time — April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ 50 — 706. — 425 50 — ...
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... Transceiver block minimum (gxb_powerdown) — power-down pulse width Receiver Supported I/O Standards Data rate (Single width, — non-PMA Direct) April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ 45 — 200 — 1200 200 — ...
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... DC gain pins for data rates = 0 dB > 10.3125 Gbps ICM 0.82 V setting V ICM V = 1.2 V ICM setting (5) April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ 1000 — 11300 1000 600 - 3250 600 ...
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... DC Gain Setting = 1 Programmable DC DC Gain gain Setting = 2 DC Gain Setting = 3 DC Gain Setting = 4 EyeQ Max Data Rate — April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ 85 ± 20% 85 ± 20% 100 ± 20% 100 ± ...
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... OCM setting 85− Ω setting 100− Ω setting Differential on-chip termination resistors 120− Ω setting 150-Ω setting April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ 2500 — 6500 2500 3125 — ...
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... XAUI, PCIe, ×4, Basic ×4 ×8 PMA and Inter-transceiver block PCS bonded transmitter mode channel-to-channel Example: skew PCIe ×8, Basic ×8 April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ Compliant 50 — 200 ...
Page 31
... ATX PLL (6G Supported Data Range / ATX PLL (10G) Supported Data Range — Transceiver-FPGA Fabric Interface Interface speed — (non-PMA Direct) April 2011 Altera Corporation –2 Industrial Speed –1 Industrial Speed Grade Grade Min Typ Max Min Typ — — 400 — ...
Page 32
... AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. April 2011 Altera Corporation –2 Industrial Speed – ...
Page 33
... Figure 1–2. Lock Time Parameters for Manual Mode r x_analogreset CDR status r x_locktodata Invalid Data r x_dataout Figure 1–3 shows the lock time parameters in automatic mode. Figure 1–3. Lock Time Parameters for Automatic Mode CDR status r x_freqlocked r x_dataout April 2011 Altera Corporation LTR t t LTR LTD_Manual t LTR_LTD_Manual LTR Invalid data t ...
Page 34
... Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part Pre- Emphasis 1st 0 1 Post-Tap Setting N/A 0.7 April 2011 Altera Corporation Table 1–28 lists the typical differential V Setting, TX Term = 85 Ω Setting (mV 170 ± 340 ± 510 ± 595 ± ...
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... N/A N/A 31 N/A N/A Table 1–30 lists the Stratix IV GX transceiver jitter specifications for all supported protocols. For protocols supported by Stratix IV GT industrial speed grade devices, refer to the Stratix IV GX –2 commercial speed grade column in April 2011 Altera Corporation V Setting 0 ...
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... Pattern = CRPAT Deterministic jitter FC-2 Pattern = CRPAT Total jitter FC-4 Pattern = CRPAT Deterministic jitter FC-4 Pattern = CRPAT Fibre Channel Receiver Jitter Tolerance (4), Deterministic jitter FC-1 Pattern = CJTPAT April 2011 Altera Corporation –2 Commercial Speed Grade Min Typ Max (3) — — 0.1 — ...
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... Total jitter at 2.5 Gbps Compliance pattern (Gen1) Total jitter at 5 Gbps (Gen2) Compliance pattern PCIe (Gen 1) Electrical Idle Detect Threshold V (15) Compliance pattern RX-IDLE-DETDIFFp-p April 2011 Altera Corporation (Note –2 Commercial Speed Grade –2× Commercial Min Typ Max Min > 0.31 > ...
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... Total jitter (peak-to-peak) Pattern = CRPAT GIGE Receiver Jitter Tolerance (8) Deterministic jitter tolerance Pattern = CJPAT (peak-to-peak) Combined deterministic and random jitter tolerance Pattern = CJPAT (peak-to-peak) April 2011 Altera Corporation (Note –3 Commercial/ –2 Commercial –2× Commercial Speed Grade Min Typ Max Min (7) — ...
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... Data Rate = 6.375 Gbps Deterministic jitter tolerance Pattern = PRBS31 BER = (peak-to-peak) -12 10 Data Rate = 6.375 Gbps Combined deterministic and Pattern=PRBS31 random jitter tolerance (peak-to-peak) BER = 10 April 2011 Altera Corporation –2 Commercial Speed Grade Min Typ Max — — 0.17 — — 0.35 > ...
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... Data Rate = 2.97 Gbps (peak-to-peak) (3G) Pattern = Single Line Scramble Color Bar Jitter Frequency = 148.5 MHz Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar April 2011 Altera Corporation (Note 1), (2) (Part –3 Commercial/ –2 Commercial Industrial and Speed Grade –2× Commercial ...
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... Gbps (G1) Pattern = CJTPAT BER = 1E-12 CPRI Transmit Jitter Generation (17) E.6.HV, E.12.HV Pattern = CJPAT Total Jitter E.6.LV, E.12.LV, E.24.LV, E.30.LV Pattern = CJTPAT April 2011 Altera Corporation (Note 1), (2) (Part –3 Commercial/ –2 Commercial Industrial and Speed Grade –2× Commercial Speed Grade ...
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... April 2011 Altera Corporation Switching Characteristics –4 Commercial/ Industrial Speed Unit Grade Min Typ Max — — 0.14 UI — — 0.17 UI > 0.66 UI > ...
Page 43
... The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification. (17) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0. (18) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1. April 2011 Altera Corporation (Note 1), ...
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... Switching Characteristics Max Min Typ Max — 0.30 — — 0.30 — 0.17 — — 0.17 — > 5 — — — 0.3 — — — April 2011 Altera Corporation Unit ...
Page 45
... The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification. (2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1. (3) Contact Altera for board and link best practices at BER = 1E-15. Table 1–32 lists the SFI-S transmitter jitter specifications for Stratix IV GT devices. ...
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... Performance –2/–2× Speed Grade –3 Speed Grade 800 700 550 500 Switching Characteristics Transceiver Transceiver Architecture in Transceiver Architecture in Transceiver Architecture in Transceiver Transceiver Architecture in Transceiver Unit –4 Speed Grade 500 MHz 450 MHz April 2011 Altera Corporation ...
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... Input clock cycle to cycle jitter (F t (4), (5) INCCJ Input clock cycle to cycle jitter (F Period Jitter for dedicated clock output (F t (6) OUTPJ_DC Period Jitter for dedicated clock output (F April 2011 Altera Corporation Parameter Min 600 600 600 40 — — — — — ...
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... Switching Characteristics Typ Max Unit — 175 ps (p-p) — 17.5 mUI (p-p) — 600 ps (p-p) — 60 mUI (p-p) — 600 ps (p-p) — 60 mUI (p-p) — 250 ps (p-p) — 25 mUI (p-p) — ±10 % specification. VCO Table 1–48 on April 2011 Altera Corporation ...
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... Resources Used Memory Mode ALUTs Single port 64×10 0 Simple dual-port 0 32×20 MLAB Simple dual-port (3) 0 64×10 ROM 64×10 0 ROM 32×20 0 April 2011 Altera Corporation (Note Resources Used –2/–2× Number of Speed Multipliers Grade 1 520 1 540 1 600 1 480 4 490 ...
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... Speed Grade 475 540 475 420 490 420 300 340 300 370 430 370 290 335 290 475 540 475 475 540 475 850 800 850 690 625 690 April 2011 Altera Corporation Unit MHz MHz MHz MHz MHz MHz MHz ps ps ...
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... For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed grade column. April 2011 Altera Corporation –2 /–2× –3 TriMatrix ...
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... MHz Configuration, Design chapter. Min Max Unit 30 — — — — — — ns — 11 (1) ns — 14 (1) ns — the TDO JPCO CCIO Typ Max Unit μA — 500 — 0.9 V Ω — < 5 — 1.030 — April 2011 Altera Corporation ...
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... HSCLK_in clock frequency) Clock boost factor Single Ended I/O (3) Standards (10) f (output HSCLK_OUT — clock frequency) April 2011 Altera Corporation Min 500 (Note 1), (2), (10) (Part 1 of 3)—Preliminary –2/–2× Speed Grade –3 Speed Grade Min Typ Max Min 5 — ...
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... April 2011 Altera Corporation Unit ...
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... Standards with Three External t t Output Resistor Networks RISE & FALL Emulated Differential I/O Standards with One External Output Resistor April 2011 Altera Corporation (Note 1), (2), (10) (Part 2 of 3)—Preliminary –2/–2× Speed Grade –3 Speed Grade Min Typ Max Min ...
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... April 2011 Altera Corporation Unit ...
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... For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed grade column. April 2011 Altera Corporation (Note 1), (2), (10) (Part 3 of 3)—Preliminary – ...
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... April 2011 Altera Corporation ...
Page 59
... Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than 1.25 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification 25 8.5 0.35 0 April 2011 Altera Corporation (Note 1), (2), Number of Data Number of Repetitions Transitions in One per 256 Data Transitions Repetition of the (4) ...
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... Switching Characteristics Sinusoidal Jitter (UI) 25.000 25.000 0.350 0.350 Frequency 20 MHz Number of DQS Delay Buffer Delay Mode (1) Chains Low 16 Low 12 Low 10 Low 8 High 12 High 10 High 8 April 2011 Altera Corporation ...
Page 61
... Note to Table 1–47: (1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –2/–2x speed grade is ± ± 39 ps. April 2011 Altera Corporation Available Phase Shift –3 –4 Speed Grade 470-590 60°, 120°, 180°, 240° ...
Page 62
... The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible. (3) The memory output clock jitter stated in 1 For the Stratix IV GT – ...
Page 63
... Symbol Output Duty Cycle I/O Timing Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus II Timing Analyzer. Excel-based I/O Timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis ...
Page 64
... Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter 1: DC and Switching Characteristics for Stratix IV Devices (Note 1) Parameter Typical 0 (default) Rising and/or falling edge delay I/O Timing Unit 100 ps 150 ps April 2011 Altera Corporation ...
Page 65
... Left/right PLL input clock frequency. HSCLK High-speed I/O block: Maximum/minimum LVDS data transfer rate f HSDR 1/TUI), non-DPA. HSDR High-speed I/O block: Maximum/minimum LVDS data transfer rate f HSDRDPA (f HSDRDPA — April 2011 Altera Corporation Definitions — — = 1/TUI), DPA. — Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 1– ...
Page 66
... Chapter 1: DC and Switching Characteristics for Stratix IV Devices Definitions t JCP JCH JCL JPSU JPH t t JPZX JPCO — (1) Switchover INPFD N PFD Reconfigurable in User Mode External Feedback — Glossary t JPXZ CLKOUT Pins f OUT_EXT f GCLK Counters f VCO VCO OUT C0..C9 RCLK April 2011 Altera Corporation ...
Page 67
... Period jitter on the general purpose I/O driven by a PLL OUTPJ_IO t Period jitter on the dedicated clock output driven by a PLL OUTPJ_DC t Signal low-to-high transition time (20-80%) RISE U — April 2011 Altera Corporation Definitions Bit Time Sampling Window RSKM RSKM 0.5 x TCCS (SW) V REF — ...
Page 68
... Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter 1: DC and Switching Characteristics for Stratix IV Devices Definitions — Changes Table 1–1, Table 1–5, Table 1–6, Table 1–24. Document Revision History 1–13, Table 1–16, Table 1–23, and April 2011 Altera Corporation ...
Page 69
... June 2009 3.1 Table 1–21, Table 1–22, Table 1–23, Table 1–25, Table 1–37, Table 1–38, Table 1–39, Table 1–40, and Table 1–44. Minor text edits. ■ April 2011 Altera Corporation Changes Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 1–67 ...
Page 70
... Minor text edits and an additional note to Table 1–26. ■ May 2008 1.0 Initial release. Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter 1: DC and Switching Characteristics for Stratix IV Devices Document Revision History Changes April 2011 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
Page 72
... Feedback Equalization (DFE)” is published. “Adaptive Equalization (AEQ)” sections to the chapter. “Power-On Reset Circuitry” and “Power-On Reset Specifications” Document Revision History section now that AN 612: Decision Dynamic Reconfiguration in sections to chapter. – 4 commercial speed grade. February 2011 Altera Corporation ...