EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 67

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Table 1–53. Glossary Table (Part 3 of 4)
April 2011 Altera Corporation
Letter
S
U
T
SW (sampling
window)
Single-ended
voltage
referenced I/O
standard
t
TCCS (channel-
to-channel-skew)
t
t
t
t
t
t
C
DUTY
FALL
INCCJ
OUTPJ_IO
OUTPJ_DC
RISE
Subject
—
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
Single-Ended Voltage Referenced I/O Standard
High-speed receiver/transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including t
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the general purpose I/O driven by a PLL
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20-80%)
0.5 x TCCS
V
V
OH
OL
RSKM
Sampling Window
Bit Time
(SW)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
V
REF
Definitions
RSKM
—
0.5 x TCCS
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
C
/w)
V
CCIO
V
SS
CO
variation
1–65