XC3S50AN-4TQG144I Xilinx Inc, XC3S50AN-4TQG144I Datasheet - Page 43

• Manufacturer Part Number: XC3S50AN-4TQG144I
• Description: IC FPGA SPARTAN-3AN50K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQG144I

• Total Ram Bits: 55296
• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• No. Of Logic Blocks: 176
• No. Of Gates: 50000
• No. Of Macrocells: 1584
• Family Type: Spartan-3AN
• No. Of Speed Grades: 4
• No. Of I/o's: 108
• Clock: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1597; XC3S50AN-4TQG144I

Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V
with the parameters used in
not confuse V
model with V
table. A fourth parameter, C
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
2. Record the time to V
3. Simulate the same signal standard with the output
4. Record the time to V
5. Compare the results of steps 2 and 4. Add (or subtract)
Simultaneously Switching Output
Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
DS557 (v4.1) April 1, 2011
Product Specification
www.xilinx.com/support/download/index.htm
driver connected to the test setup shown in
Use parameter values V
C
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V
and V
load.
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment
yield the worst-case delay of the PCB trace.
REF
is zero.
MEAS
REF
REF
REF
values) or capacitive value to represent the
, R
(the input-switching threshold) from the
(the termination voltage) from the IBIS
REF
, and V
M
MEAS
.
REF
T
Table 30
, R
.
MEAS
, is always zero. The four
T
, and V
) correspond directly
(V
REF
T
M
, R
from
, R
T
, and V
(Table
REF
Table
Figure
, C
M
29) to
REF
CCO
). Do
30.
www.xilinx.com
11.
,
Spartan-3AN FPGA Family: DC and Switching Characteristics
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 31
guidelines. For each device/package combination,
provides the number of equivalent V
equivalent number of pairs is based on characterization and
may not match the physical number of pairs. For each
output signal standard and drive strength,
recommends the maximum number of SSOs, switching in
the same direction, allowed per V
I/O bank. The guidelines in
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from
Table 32
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (TQ) is
lower than for ball grid array packages (FG) due to the
larger lead inductance of the quad-flat packages. Ball grid
array packages are recommended for applications with a
large number of simultaneously switching outputs.
Table 31: Equivalent V
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Device
SSO
MAX
and
to calculate the maximum number of SSOs
/IO Bank =
Table 32
TQG144 FTG256 FGG400 FGG484 FGG676
2
–
–
–
–
provide the essential SSO
Table 31
CCO
3
4
4
–
–
Table 32
/GND Pairs per Bank
Package Style
CCO
x
Table 32
–
–
5
–
–
CCO
are categorized by
/GND pair within an
Table 31
/GND pairs. The
Table 32
–
–
–
5
6
and
Table 31
–
–
–
–
9
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