XC3S50AN-4TQG144I Xilinx Inc, XC3S50AN-4TQG144I Datasheet - Page 86

• Manufacturer Part Number: XC3S50AN-4TQG144I
• Description: IC FPGA SPARTAN-3AN50K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQG144I

• Total Ram Bits: 55296
• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• No. Of Logic Blocks: 176
• No. Of Gates: 50000
• No. Of Macrocells: 1584
• Family Type: Spartan-3AN
• No. Of Speed Grades: 4
• No. Of I/o's: 108
• Clock: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1597; XC3S50AN-4TQG144I

User I/Os by Bank
Table 71
package. The AWAKE pin is counted as a dual-purpose I/O. The XC3S50AN FPGA in the FTG256 package has 51
unconnected balls, labeled with an N.C. type. These pins are also indicated in
Table 71: User I/Os Per Bank on XC3S50AN in the FTG256 Package
Table 72: User I/Os Per Bank on XC3S200AN and XC3S400AN in the FTG256 Package
DS557 (v4.1) April 1, 2011
Product Specification
Top
Right
Bottom
Left
Top
Right
Bottom
Left
Package
Package
Edge
Edge
Total
Total
and
Table 72
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
indicate how the available user-I/O pins are distributed between the four I/O banks on the FTG256
Maximum I/Os
Maximum I/Os
144
195
40
32
40
32
47
50
48
50
I/O
I/O
21
12
15
53
27
11
30
69
5
1
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INPUT
INPUT
20
21
7
5
2
6
6
6
2
7
All Possible I/O Pins by Type
All Possible I/O Pins by Type
Spartan-3AN FPGA Family: Pinout Descriptions
Figure
DUAL
DUAL
21
26
30
21
52
1
4
0
1
0
20.
VREF
VREF
15
21
3
3
6
3
5
5
6
5
CLK
CLK
30
32
8
8
6
8
8
8
8
8
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